Submicrometer radius and highly confined plasmonic ring resonator filters based on hybrid metal-oxide-semiconductor waveguide

2012 ◽  
Vol 37 (21) ◽  
pp. 4564 ◽  
Author(s):  
Hong-Son Chu ◽  
Yuriy Akimov ◽  
Ping Bai ◽  
Er-Ping Li
Keyword(s):  
Metal Oxide ◽  
Ring Resonator ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Hybrid Metal Oxide ◽  
Resonator Filters

scholarly journals Numerical analysis of optical phase modulator operating at 2 μm wavelength using graphene/III-V hybrid metal-oxide-semiconductor capacitor

2021 ◽  
Author(s):  
Tipat Piyapatarakul ◽  
Hanzhi Tang ◽  
Kasidit Toprasertpong ◽  
Shinichi TAKAGI ◽  
Mitsuru TAKENAKA
Keyword(s):  
Metal Oxide ◽  
High Efficiency ◽  
Chemical Potential ◽  
Optical Fiber Communication ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Single Layer Graphene ◽  
Phase Modulator ◽  
Optical Phase ◽  
Hybrid Metal Oxide

Abstract We propose an optical phase modulator with a hybrid metal-oxide-semiconductor (MOS) capacitor, consisting of single-layer graphene and III-V semiconductor waveguide. The proposed modulator is numerically analyzed in conjunction with the surface conductivity model of graphene. Since the absorption of graphene at a 2 µm wavelength can be suppressed by modulating the chemical potential of graphene with the practical gate bias, the phase modulation efficiency is predicted to be 0.051 V·cm with a total insertion loss of 0.85 dB when an n-InGaAs waveguide is used, showing the feasibility of the low-loss, high-efficiency graphene/III-V hybrid MOS optical phase modulator, which is useful in the future 2-µm optical fiber communication band.

Optical modulator using metal-oxide-semiconductor type Si ring resonator

2009 ◽  
Vol 16 (3) ◽  
pp. 247-251 ◽  
Author(s):  
Yoshiteru Amemiya ◽  
Tomohiro Tokunaga ◽  
Yuichiro Tanushi ◽  
Shin Yokoyama
Keyword(s):  
Metal Oxide ◽  
Ring Resonator ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Optical Modulator ◽  
Semiconductor Type

Polycrystalline silicon ring resonator photodiodes in a bulk complementary metal-oxide-semiconductor process

2014 ◽  
Vol 39 (4) ◽  
pp. 1061 ◽  
Author(s):  
Karan K. Mehta ◽  
Jason S. Orcutt ◽  
Jeffrey M. Shainline ◽  
Ofer Tehar-Zahav ◽  
Zvi Sternberg ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Polycrystalline Silicon ◽  
Ring Resonator ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Semiconductor Process

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

2020 ◽  
Vol 13 ◽  
Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu
Keyword(s):  
Monte Carlo ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Cmos Inverter ◽  
Back Gate ◽  
Random Dopant Fluctuation ◽  
Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

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