Silicon nano pin arrays with heights of 1.3-3.66um and diameter of 315-899nm, are fabricated by CsCl self-assemble for CsCl nano islands for mask and ICP etching for silicon pins. CsCl film is firstly deposited on the wafer by thermal evaporation and putted in the humid controlled environment to be developed to the CsCl islands with diameter of 341-915 nm as self-assembled technology. Then the ICP etching with SF6, CCl4, He gas is introduced to make the silicon nano pin by the mask of CsCl nano islands, and the silicon nano pins with the different height of 1.3-3.66 um are finished for field emission. The gated FEA templates are fabricated by photolithography process and the lift-off technology with Ti-Si film as the gate electrodes. The final template for field emission has the silicon nano pins with diameters of 31.7 nm on top, Ti-Ag film with thickness of 105nm and gate holes of 30um in diameter, and SU8 resist insulator structure with thickness of 4um and holes of 10um in diameter. The optimization of the fabrication process and the performance for the configuration will be made.
Low-loss titanium dioxide waveguides and resonators using a dielectric lift-off fabrication process