Numerical investigation into the output performance of the silicon Raman laser based on silicon-on-insulator waveguide pumped by 2 μm lasers

2021 ◽  
Author(s):  
Zhenhua Shao ◽  
Xuanxi Li ◽  
Haotian Wang ◽  
Heyuan Zhu ◽  
Deyuan SHEN
Keyword(s):  
Numerical Investigation ◽  
Raman Laser ◽  
Silicon On Insulator ◽  
Output Performance

Semi-analytical model of Raman generation in silicon-on-insulator rib waveguide with DBR/F-P resonator

2013 ◽  
Vol 21 (4) ◽  
Author(s):  
A. Tyszka-Zawadzka ◽  
P. Szczepański ◽  
A. Mossakowska-Wyszyńska ◽  
M. Karpierz ◽  
M. Bugaj
Keyword(s):  
Pump Power ◽  
Numerical Solutions ◽  
Analytical Formula ◽  
Raman Laser ◽  
Silicon On Insulator ◽  
Photon Absorption ◽  
Pump Field ◽  
Rib Waveguide ◽  
System Parameters ◽  
Field Distributions

AbstractAn approximate method of modelling of Raman generation in silicon-on-insulator (SOI) rib waveguide with DBR/F-P resonator including spatial field distribution and nonlinear effects such as Raman amplification and two photon absorption (TPA), is developed. In threshold analysis of steady-state Raman laser operation, an analytical formula relating threshold pump power to the system parameters is obtained. The analysis of the above threshold operation is based on an energy theorem. In exact energy conservation relation, we approximate the Stokes field distributions by that existing at the threshold, whereas the approximate pump field distributions are obtained by integrating the equations for the pump signal using the linear (threshold) pump field distributions and the threshold Stokes field distributions. An approximate, semi-analytical expression related the Raman output power to the pump power and system parameters is derived. Our calculations remain in a good agreement with the exact numerical solutions.

scholarly journals Prospect of CW Raman Laser in Silicon- on- Insulator Nano-Waveguides

2020 ◽  
Vol 18 (45) ◽  
pp. 9-20
Author(s):  
Zainab Salam Khaleefia ◽  
Sh. S. Mahdi ◽  
S. Kh. Yaseen
Keyword(s):  
Communication Systems ◽  
Continuous Wave ◽  
Raman Laser ◽  
Silicon On Insulator ◽  
Photon Absorption ◽  
Lasing Threshold ◽  
Free Carrier Absorption ◽  
Carrier Absorption ◽  
Raman Lasing ◽  
On Chip

Numerical analysis predicts that continuous-wave (CW) Raman lasing is possible in Silicon-On-insulator (SOI) nano-waveguides, despite of presence of free carrier absorption. The scope of this paper lies on lasers for communication systems around 1550 nm wavelength. Two types of waveguide structures Strip and Rib waveguides have been incorporated. The waveguide structures have designed to be 220 nm in height. Three different widths of (350, 450, 1000) nm were studied. The dependence of lasing of the SOI Raman laser on effective carrier lifetime was discussed, produced by tow photon absorption. At telecommunication wavelength of 1550 nm, Raman lasing threshold was calculated to be 1.7 mW in Rib SOI waveguide with dimensions width (W= 450 nm) and Length (L= 25 mm). The obtained Raman lasing is the lowest reported value at relatively high reflectivities. Raman laser in SOI nano-waveguides presents the important step towards integrated on-chip optoelectronic devices.

Design and modeling a mid infrared Raman laser on silicon-on-insulator

2020 ◽  
Author(s):  
Mohammad Ahmadi ◽  
Loyc Bordiu ◽  
Wei Shi ◽  
Sophie Larochelle
Keyword(s):  
Raman Laser ◽  
Silicon On Insulator ◽  
Mid Infrared

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

In Situ microscopy of the anodic etching of silicon

1995 ◽  
Vol 53 ◽  
pp. 232-233
Author(s):  
Frances M. Ross ◽  
Peter C. Searson
Keyword(s):  
Composite Structures ◽  
High Surface ◽  
High Surface Area ◽  
Chemical Properties ◽  
Selective Etching ◽  
Silicon On Insulator ◽  
Second Phase ◽  
Porous Layers ◽  
New Class ◽  
Porous Semiconductors

Porous semiconductors represent a relatively new class of materials formed by the selective etching of a single or polycrystalline substrate. Although porous silicon has received considerable attention due to its novel optical properties1, porous layers can be formed in other semiconductors such as GaAs and GaP. These materials are characterised by very high surface area and by electrical, optical and chemical properties that may differ considerably from bulk. The properties depend on the pore morphology, which can be controlled by adjusting the processing conditions and the dopant concentration. A number of novel structures can be fabricated using selective etching. For example, self-supporting membranes can be made by growing pores through a wafer, films with modulated pore structure can be fabricated by varying the applied potential during growth, composite structures can be prepared by depositing a second phase into the pores and silicon-on-insulator structures can be formed by oxidising a buried porous layer. In all these applications the ability to grow nanostructures controllably is critical.

Analysis of Silicon-On-Insulator Structures Formed By Oxygen Ion Implantation

1985 ◽  
Vol 43 ◽  
pp. 300-301
Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
A. Mogro-Campero ◽  
R. P. Love
Keyword(s):  
Ion Implantation ◽  
Single Crystal ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Dose ◽  
Crystal Silicon ◽  
Oxygen Ion ◽  
Oxygen Ion Implantation

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

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