Ultra-low Jitter Frequency Stabilized Mode-locked Laser

Author(s):  
Ibrahim Ozdur ◽  
Mehmetcan Akbulut ◽  
Nazanin Hoghooghi ◽  
Dimitrios Mandridis ◽  
Sarper Ozharar ◽  
...  
Keyword(s):  
2003 ◽  
Author(s):  
Alan M. Braun ◽  
Bradford B. Price ◽  
Daniel W. Bechtle ◽  
Martin H. Kwakernaak ◽  
Joseph H. Abeles ◽  
...  

Author(s):  
Yin S Ng ◽  
William Lo ◽  
Kenneth Wilsher

Abstract We present an overview of Ruby, the latest generation of backside optical laser voltage probing (LVP) tools [1, 2]. Carrying over from the previous generation of IDS2700 systems, Ruby is capable of measuring waveforms up to 15GHz at low core voltages 0.500V and below. Several new optical capabilities are incorporated; these include a solid immersion lens (SIL) for improved imaging resolution [3] and a polarization difference probing (PDP) optical platform [4] for phase modulation detection. New developments involve Jitter Mitigation, a scheme that allows measurements of jittery signals from circuits that are internally driven by the IC’s onboard Phase Locked Loop (PLL). Additional timing features include a Hardware Phase-Locked Loop (HWPLL) scheme for improved locking of the LVP’s Mode-Locked Laser (MLL) to the tester clock as well as a clockless scheme to improve the LVP’s usefulness and user friendliness. This paper presents these new capabilities and compares these with those of the previous generation of LVP systems [5, 6].


2006 ◽  
Vol 49 (2) ◽  
pp. 131-140 ◽  
Author(s):  
Michael J. Chan ◽  
Adam Postula ◽  
Yong Ding ◽  
Lech Jozwiak
Keyword(s):  

2021 ◽  
pp. 1-1
Author(s):  
Dongmei Huang ◽  
Feng Li ◽  
Zihao Cheng ◽  
Xinhuan Feng ◽  
P. K. A. Wai

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 177
Author(s):  
Dongjun Park ◽  
Sungwook Choi ◽  
Jongsun Kim

An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast lock time of 15 reference clock cycles while maintaining a wide detection range and high resolution. The proposed offset-free TDC also uses a correlated double sampling technique to remove mismatch and offset issues, resulting in low jitter characteristics. After the MDLL is quickly locked, the TDC is turned off, and it goes into delta-sigma modulator (DSM)-based sequential tracking mode to reduce power consumption and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed MDLL occupies an active area of 0.043 mm2 and generates a 2.4-GHz output clock from a 75-MHz reference clock (multiplication factor N = 32). It achieves an effective peak-to-peak jitter of 9.4 ps and consumes 3.3 mW at 2.4 GHz.


Sign in / Sign up

Export Citation Format

Share Document