Ultra-low Jitter Frequency Stabilized Mode-locked Laser

2009 ◽  
Author(s):  
Ibrahim Ozdur ◽  
Mehmetcan Akbulut ◽  
Nazanin Hoghooghi ◽  
Dimitrios Mandridis ◽  
Sarper Ozharar ◽  
...  
Keyword(s):  
Low Jitter ◽  
Mode Locked Laser

Compact high-power low-jitter semiconductor mode-locked laser module for photonic A/D converter applications

2003 ◽  
Author(s):  
Alan M. Braun ◽  
Bradford B. Price ◽  
Daniel W. Bechtle ◽  
Martin H. Kwakernaak ◽  
Joseph H. Abeles ◽  
...  
Keyword(s):  
High Power ◽  
Low Jitter ◽  
Laser Module ◽  
Mode Locked Laser

Next Generation Laser Voltage Probing

2008 ◽  
Author(s):  
Yin S Ng ◽  
William Lo ◽  
Kenneth Wilsher
Keyword(s):  
Phase Modulation ◽  
Phase Locked Loop ◽  
Next Generation ◽  
Solid Immersion Lens ◽  
User Friendliness ◽  
New Developments ◽  
Polarization Difference ◽  
Previous Generation ◽  
Mode Locked Laser ◽  
Optical Laser

Abstract We present an overview of Ruby, the latest generation of backside optical laser voltage probing (LVP) tools [1, 2]. Carrying over from the previous generation of IDS2700 systems, Ruby is capable of measuring waveforms up to 15GHz at low core voltages 0.500V and below. Several new optical capabilities are incorporated; these include a solid immersion lens (SIL) for improved imaging resolution [3] and a polarization difference probing (PDP) optical platform [4] for phase modulation detection. New developments involve Jitter Mitigation, a scheme that allows measurements of jittery signals from circuits that are internally driven by the IC’s onboard Phase Locked Loop (PLL). Additional timing features include a Hardware Phase-Locked Loop (HWPLL) scheme for improved locking of the LVP’s Mode-Locked Laser (MLL) to the tester clock as well as a clockless scheme to improve the LVP’s usefulness and user friendliness. This paper presents these new capabilities and compares these with those of the previous generation of LVP systems [5, 6].

A bang-bang PLL employing dynamic gain control for low jitter and fast lock times

2006 ◽  
Vol 49 (2) ◽  
pp. 131-140 ◽  
Author(s):  
Michael J. Chan ◽  
Adam Postula ◽  
Yong Ding ◽  
Lech Jozwiak
Keyword(s):  
Gain Control ◽  
Low Jitter ◽  
Dynamic Gain

Time domain discrete Fourier domain mode locked laser with k-space uniform comb lines

2021 ◽  
pp. 1-1
Author(s):  
Dongmei Huang ◽  
Feng Li ◽  
Zihao Cheng ◽  
Xinhuan Feng ◽  
P. K. A. Wai
Keyword(s):  
Time Domain ◽  
Fourier Domain ◽  
Mode Locked Laser

scholarly journals A Fast Lock All-Digital MDLL Using a Cyclic Vernier TDC for Burst-Mode Links

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 177
Author(s):  
Dongjun Park ◽  
Sungwook Choi ◽  
Jongsun Kim
Keyword(s):  
Sampling Technique ◽  
Cmos Process ◽  
Detection Range ◽  
Delay Locked Loop ◽  
Delta Sigma Modulator ◽  
Correlated Double Sampling ◽  
Delta Sigma ◽  
Fast Power ◽  
Low Jitter ◽  
Reference Clock

An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast lock time of 15 reference clock cycles while maintaining a wide detection range and high resolution. The proposed offset-free TDC also uses a correlated double sampling technique to remove mismatch and offset issues, resulting in low jitter characteristics. After the MDLL is quickly locked, the TDC is turned off, and it goes into delta-sigma modulator (DSM)-based sequential tracking mode to reduce power consumption and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed MDLL occupies an active area of 0.043 mm2 and generates a 2.4-GHz output clock from a 75-MHz reference clock (multiplication factor N = 32). It achieves an effective peak-to-peak jitter of 9.4 ps and consumes 3.3 mW at 2.4 GHz.

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