A New network multiplier using modified high order encoder and optimized hybrid adder in CMOS technology
1978 ◽
Vol 36
(1)
◽
pp. 330-331
Keyword(s):
1987 ◽
Vol 45
◽
pp. 384-385
Keyword(s):
1993 ◽
Vol 51
◽
pp. 692-693