Capacitance-Voltage and Drive-Level–Capacitance Profiling

2018 ◽  
pp. 85-113
Author(s):  
Jennifer T. Heath
Keyword(s):  
Drive Level ◽  
Capacitance Voltage

Influence of Traps on Carrier Concentration Profiles Measured by Capacitance-Voltage and Drive Level Profiling in CIGSe-based Heterojunctions

2005 ◽  
Vol 865 ◽  
Author(s):  
P. Zabierowskia ◽  
M. Ćwila ◽  
M. Edoffb
Keyword(s):  
Detailed Analysis ◽  
Carrier Concentration ◽  
Minority Carrier ◽  
Low Frequency ◽  
Drive Level ◽  
Concentration Profiles ◽  
Capacitance Voltage ◽  
Carrier Traps ◽  
Capacitance Transient

AbstractDetailed analysis of drive level capacitance, capacitance voltage characteristics and capacitance transient was carried out to elucidate the influence of N1 defects on carrier concentration profiles. The type of hysteresis observed in CV curves proves that N1 traps originate from close-to-interface minority carrier traps. We show that in the presence of these states one must be careful while interpreting DLCP data. It was found that due to the incomplete charging of N1 defects, low frequency drive level profiles may give erroneous defects densities.

Laser Engineering of Barrier Structures Based on Solid Solution ZnCdHgTe.

2002 ◽  
Vol 719 ◽  
Author(s):  
Galina Khlyap
Keyword(s):  
Room Temperature ◽  
Film Surface ◽  
Charge Carriers ◽  
Barrier Structure ◽  
Free Charge ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Laser Engineering ◽  
Charged Defects ◽  
Epilayer Surface

AbstractRoom-temperature electric investigations carried out in CO2-laser irradiated ZnCdHgTe epifilms revealed current-voltage and capacitance-voltage dependencies typical for the metal-semiconductor barrier structure. The epilayer surface studies had demonstrated that the cell-like relief has replaced the initial tessellated structure observed on the as-grown samples. The detailed numerical analysis of the experimental measurements and morphological investigations of the film surface showed that the boundaries of the cells formed under the laser irradiation are appeared as the regions of accumulation of derived charged defects of different type of conductivity supplying free charge carriers under the applied electric field.

HVPE-GROWN AlGaN/GaN HEMTs

2003 ◽  
Vol 764 ◽  
Author(s):  
B. Luo ◽  
F. Ren ◽  
M. A. Mastro ◽  
D. Tsvetkov ◽  
A. Pechnikov ◽  
...  
Keyword(s):  
High Electron Mobility Transistors ◽  
Hydride Vapor Phase Epitaxy ◽  
Root Mean Square Roughness ◽  
High Electron ◽  
Electron Mobility Transistors ◽  
Current Collapse ◽  
Collapse Characteristics ◽  
Capacitance Voltage ◽  
Source Current ◽  
Measurement Area

AbstractHigh quality undoped AlGaN/GaN high electron mobility transistors(HEMTs) structures have been gorwn by Hydride Vapor Phase Epitaxy (HVPE). The morphology of the films grown on Al2O3 substrates is excellent with root-mean-square roughness of ∼0.2nm over 10×10μm2 measurement area. Capacitance-voltage measurements show formation of dense sheet of charge at the AlGaN/GaN interface. HEMTs with 1μm gate length fabricated on these structures show transconductances in excess of 110 mS/mm and drain-source current above 0.6A/mm. Gate lag measurements show similar current collapse characteristics to HEMTs fabricated in MBE- or MOCVD grown material.

Nanoprobing Applications with Capacitance-Voltage and Pulsed Current-Voltage Measurements for Device Failure Analysis

2015 ◽  
Author(s):  
LiLung Lai ◽  
Nan Li ◽  
Qi Zhang ◽  
Tim Bao ◽  
Robert Newton
Keyword(s):  
Failure Analysis ◽  
High Speed ◽  
Pulsed Current ◽  
Electrical Measurements ◽  
Device Failure ◽  
Mos Devices ◽  
Atomic Force ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Rising Time

Abstract Owing to the advancing progress of electrical measurements using SEM (Scanning Electron Microscope) or AFM (Atomic Force Microscope) based nanoprober systems on nanoscale devices in the modern semiconductor laboratory, we already have the capability to apply DC sweep for quasi-static I-V (Current-Voltage), high speed pulsing waveform for the dynamic I-V, and AC imposed for C-V (Capacitance-Voltage) analysis to the MOS devices. The available frequency is up to 100MHz at the current techniques. The specification of pulsed falling/rising time is around 10-1ns and the measurable capacitance can be available down to 50aF, for the nano-dimension down to 14nm. The mechanisms of dynamic applications are somewhat deeper than quasi-static current-voltage analysis. Regarding the operation, it is complicated for pulsing function but much easy for C-V. The effective FA (Failure Analysis) applications include the detection of resistive gate and analysis for abnormal channel doping issue.

Nanoprobe Characterization of Soft SRAM bit Fails in Advanced Technologies

2019 ◽  
Author(s):  
Satish Kodali ◽  
Chen Zhe ◽  
Chong Khiam Oh
Keyword(s):  
Yield Loss ◽  
Performance Metrics ◽  
Root Cause ◽  
Advanced Technologies ◽  
Capacitance Voltage ◽  
Defect Localization ◽  
Cv Measurements ◽  
Lightly Doped Drain ◽  
Dc Characterization

Abstract Nanoprobing is one of the key characterization techniques for soft defect localization in SRAM. DC transistor performance metrics could be used to identify the root cause of the fail mode. One such case report where nanoprobing was applied to a wafer impacted by significant SRAM yield loss is presented in this paper where standard FIB cross-section on hard fail sites and top down delayered inspection did not reveal any obvious defects. The authors performed nanoprobing DC characterization measurements followed by capacitance-voltage (CV) measurements. Two probe CV measurement was then performed between the gate and drain of the device with source and bulk floating. The authors identified valuable process marginality at the gate to lightly doped drain overlap region. Physical characterization on an inline split wafer identified residual deposits on the BL contacts potentially blocking the implant. Enhanced cleans for resist removal was implemented as a fix for the fail mode.

dC/dV and CV Characterization of Gate Resistance Defects in eDRAM Circuits

2013 ◽  
Author(s):  
Sweta Pendyala ◽  
Dave Albert ◽  
Katherine Hawkins ◽  
Michael Tenney
Keyword(s):  
Deep Submicron ◽  
Work Flow ◽  
Localization Technique ◽  
Characterization Techniques ◽  
Capacitance Voltage ◽  
Gate Resistance

Abstract Resistive gate defects are unusual and difficult to detect with conventional techniques [1] especially on advanced devices manufactured with deep submicron SOI technologies. An advanced localization technique such as Scanning Capacitance Imaging is essential for localizing these defects, which can be followed by DC probing, dC/dV, CV (Capacitance-Voltage) measurements to completely characterize the defect. This paper presents a case study demonstrating this work flow of characterization techniques.

Nanoscale Capacitance and Capacitance-Voltage Curves for Advanced Characterization of Electrical Properties of Si and GaN Structures Using Scanning Microwave Impedance Microscopy

2016 ◽  
Author(s):  
Stuart Friedman ◽  
Oskar Amster ◽  
Yongliang Yang ◽  
Fred Stanke
Keyword(s):  
Process Development ◽  
Advanced Characterization ◽  
Electrical Measurement ◽  
Depletion Layer ◽  
Doped Semiconductors ◽  
Force Microscopy ◽  
Nano Scale ◽  
Capacitance Voltage ◽  
Systematic Response ◽  
Lock In

Abstract The use of Atomic Force Microscopy (AFM) electrical measurement modes is a critical tool for the study of semiconductor devices and process development. A relatively new electrical mode, scanning microwave impedance microscopy (sMIM), measures a material’s change in permittivity and conductivity at the scale of an AFM probe tip [1]. sMIM provides the real and imaginary impedance (Re(Z) and Im(Z)) of the probe-sample interface. By measuring the reflected microwave signal as a sample of interest is imaged with an AFM, we can in parallel capture the variations in permittivity and conductivity and, for doped semiconductors, variations in the depletion-layer geometry. An existing technique for characterizing doped semiconductors, scanning capacitance microscopy, modulates the tip-sample bias and detects the tip-sample capacitance with a lock-in amplifier. A previous study compares sMIM to SCM and highlights the additional capabilities of sMIM [2], including examples of nano-scale capacitance-voltage curves. In this paper we focus on the detailed mechanisms and capabilities of the nano-scale C-V curves and the ability to extract semiconductor properties from them. This study includes analytical and finite element modeling of tip bias dependent depletion-layer geometry and impedance. These are compared to experimental results on reference samples for both doped Si and GaN doped staircases to validate the systematic response of the sMIM-C (capacitive) channel to the doping concentration.

Extending Electrical Scanning Probe Microscopy Measurements of Semiconductor Devices Using Microwave Impedance Microscopy

2015 ◽  
Author(s):  
Benedict Drevniok ◽  
St. John Dixon-Warren ◽  
Oskar Amster ◽  
Stuart L Friedman ◽  
Yongliang Yang
Keyword(s):  
Scanning Probe Microscopy ◽  
Semiconductor Devices ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Scanning Probe ◽  
Cross Sectional ◽  
Probe Microscopy ◽  
Dopant Profiling ◽  
Capacitance Voltage

Abstract Scanning microwave impedance microscopy was used to analyze a CMOS image sensor sample to reveal details of the dopant profiling in planar and cross-sectional samples. Sitespecific capacitance-voltage spectroscopy was performed on different regions of the samples.

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