Physically Unclonable Functions: A Window into CMOS Process Variations

2017 ◽  
pp. 207-268
Keyword(s):  
Process Variations ◽  
Cmos Process ◽  
Physically Unclonable Functions ◽  
Cmos Process Variations

LOW-POWER, PARALLEL INTERFACE WITH CONTINUOUS-TIME ADAPTIVE PASSIVE EQUALIZER AND CROSSTALK CANCELLATION

2005 ◽  
Vol 15 (02) ◽  
pp. 459-476
Author(s):  
C. PATRICK YUE ◽  
JAEJIN PARK ◽  
RUIFENG SUN ◽  
L. RICK CARLEY ◽  
FRANK O'MAHONY
Keyword(s):  
Low Power ◽  
Electromagnetic Interference ◽  
Continuous Time ◽  
High Speed ◽  
High Performance ◽  
Process Variations ◽  
Cmos Process ◽  
Power Circuit ◽  
Crosstalk Cancellation ◽  
Circuit Components

This paper presents the low-power circuit techniques suitable for high-speed digital parallel interfaces each operating at over 10 Gbps. One potential application for such high-performance I/Os is the interface between the channel IC and the magnetic read head in future compact hard disk systems. First, a crosstalk cancellation technique using a novel data encoding scheme is introduced to suppress electromagnetic interference (EMI) generated by the adjacent parallel I/Os . This technique is implemented utilizing a novel 8-4-PAM signaling with a data look-ahead algorithm. The key circuit components in the high-speed interface transceiver including the receive sampler, the phase interpolator, and the transmitter output driver are described in detail. Designed in a 0.13-μm digital CMOS process, the transceiver consumes 310 mW per 10-Gps channel from a I-V supply based on simulation results. Next, a 20-Gbps continuous-time adaptive passive equalizer utilizing on-chip lumped RLC components is described. Passive equalizers offer the advantages of higher bandwidth and lower power consumption compared with conventional designs using active filter. A low-power, continuous-time servo loop is designed to automatically adjust the equalizer frequency response for the optimal gain compensation. The equalizer not only adapts to different channel characteristics, but also accommodates temperature and process variations. Implemented in a 0.25-μm, 1P6M BiCMOS process, the equalizer can compensate up to 20 dB of loss at 10 GHz while only consumes 32 mW from a 2.5-V supply.

A New Sub-1 Volt 17ppm/°C Offset-Insensitive Resistorless Switched-Capacitor Bandgap Voltage Reference

2020 ◽  
pp. 2150029
Author(s):  
Emad Ebrahimi ◽  
Maliheh Arabnasery
Keyword(s):  
Process Variations ◽  
Voltage Divider ◽  
Cmos Technology ◽  
Reference Voltage ◽  
Cmos Process ◽  
Switched Capacitor ◽  
Voltage Reference ◽  
Op Amp ◽  
Offset Voltage ◽  
Bandgap Voltage Reference

A new PVT compensated voltage reference is presented by using switched-capacitor (S.C.) technique. In the proposed bandgap voltage reference (BGR), a p–n junction is biased with different currents during two different phases and required PTAT and CTAT voltages generated and held by two capacitors. Using a capacitive voltage divider, the PTAT voltage is weighted such that the sub-1V bandgap voltage is achievable. In order to cancel the effect of op-amp offset and to relax the design of op-amp, the offset voltage of the op-amp is sampled by a capacitor during a specified phase and inversely is added to the final bandgap voltage in next phase. The analysis of the proposed S.C. BGR is supplemented by simulation of a 0.5-V BGR with 28[Formula: see text][Formula: see text][Formula: see text]W power consumption in a standard 0.18[Formula: see text][Formula: see text][Formula: see text]m CMOS technology. Simulation results show that the average temperature coefficient of the S.C. BGR is 17[Formula: see text]ppm/∘C and it is robust against the process variations. Applying an arbitrary 100-mV op-amp offset results in a lower than 1.1[Formula: see text]mV deviation in generated reference voltage. Due to the better matching of MIM capacitors in CMOS process (rather than resistors used in conventional BGR) the proposed S.C. bandgap provides good accuracy without any post trimming. Monte–Carlo analysis shows that [Formula: see text]/[Formula: see text] of the generated reference voltage is as low as 0.7%. The sensitivity of the proposed BGR to supply variation is also less than 1%/V.

3.48-nW 58.4ppm/∘C Sub-threshold CVR with Four Transistors and Two Resistors

2021 ◽  
Author(s):  
Mohammadreza Rasekhi ◽  
Emad Ebrahimi ◽  
Hamed Aminzadeh
Keyword(s):  
Process Variations ◽  
Mean Value ◽  
Absolute Temperature ◽  
Reference Voltage ◽  
Cmos Process ◽  
Voltage Reference ◽  
Ultra Low Power ◽  
Low Power Cmos ◽  
Simulation Results ◽  
Cmos Voltage Reference

In this paper, an ultra-low power CMOS voltage reference capable of operating at sub-1[Formula: see text]V input supply is proposed. Four transistors biased in weak inversion are used to generate the required complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages of the proposed circuit. Self-biasing of nature of the proposed configuration in the form of operational amplifier (opamp)-free ensure nano-power operation and eliminate the need for lateral bipolar junction transistors (BJTs) and offset cancelation techniques. A prototype of the circuit is designed and simulated in a standard 0.18-[Formula: see text]m CMOS process. Post-layout simulation results show that the circuit generates a reference voltage of 494[Formula: see text]mV with temperature coefficient (TC) of 58.4[Formula: see text]ppm/∘C across [Formula: see text]C to 85∘C; while the consuming power is lowered to 3.48[Formula: see text]nW at the minimum supply of 0.8[Formula: see text]V. The line sensitivity is 0.7%/V for the supply voltages from 0.8[Formula: see text]V to 1.8[Formula: see text]V, whereas the power supply ripple rejection (PSRR) is [Formula: see text]49.06[Formula: see text]dB at 1[Formula: see text]Hz. Monte Carlo simulation results of the voltage reference show a mean value of 497.2[Formula: see text]mV with [Formula: see text]/[Formula: see text] of 1.7%, demonstrating the robustness of the generated reference voltage against the process variations and mismatch.

scholarly journals Low-Power Two-Phase Clocking Adiabatic PUF Circuit

Electronics ◽  
2021 ◽  
Vol 10 (11) ◽  
pp. 1258
Author(s):  
Câncio Monteiro ◽  
Yasuhiro Takahashi
Keyword(s):  
Low Power ◽  
Supply Voltage ◽  
Process Variations ◽  
The Body ◽  
Cmos Process ◽  
Clock Signal ◽  
Process Technology ◽  
Two Phase ◽  
Ambient Temperatures ◽  
Start Up

Internet of Things (IoT) has enabled battery-powered devices to transmit sensitive data, while presenting high power consumption and security issues. To address these challenges, adiabatic-based physical unclonable functions (PUFs) offer a promising solution for low-power and secure IoT device applications. In this study, we propose a novel low-power two-phase clocking adiabatic PUF. The proposed adiabatic PUF utilizes a trapezoidal power clock signal with a time-ramped voltage to achieve an improved energy efficiency and reliable start-up PUF behavior. Static CMOS logic is employed to produce stable challenge-response pairs (CRPs) in the adiabatic mode. The pull-down network is designed to control the PUF cell to charge and discharge its output nodes with a constant supply current during secure key generation. The body effect of PMOS transistors, ambient temperatures, and CMOS process variations are investigated to examine the uniqueness and reliability of the proposed work. The proposed adiabatic PUF is simulated using 0.18 µm CMOS process technology with a supply voltage of 1.8 V. The uniqueness and reliability of the proposed adiabatic PUF are 49.82% and 99.47%, respectively. In addition, it requires a start-up power of 0.47 µW and consumes an energy of 15.98 fJ/bit/cycle at the reference temperature of 27 °C.

scholarly journals A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 530
Author(s):  
Stefan Pechmann ◽  
Timo Mai ◽  
Matthias Völkel ◽  
Mamathamba K. Mahadevaiah ◽  
Eduardo Perez ◽  
...  
Keyword(s):  
Voltage Drop ◽  
Random Access ◽  
Process Variations ◽  
Resistive Random Access Memory ◽  
Cmos Process ◽  
Programming System ◽  
Analog Memory ◽  
Wide Range ◽  
Multi Level ◽  
New Memory Technology

In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.

scholarly journals System-on-chip sensor fusion front-end self-healing design for network-on-chip digital communications

2017 ◽  
Author(s):  
Emmanuel Seaman ◽  
Jason Du
Keyword(s):  
Sensor Fusion ◽  
Data Storage ◽  
Communication Systems ◽  
High Speed ◽  
Process Variations ◽  
Cmos Technology ◽  
Network On Chip ◽  
Cmos Process ◽  
Self Healing ◽  
On Chip

With the ultra-scaling of CMOS technology, high-speed and low-power millimeter-wave communication systems for network-on-chip have been attracting more and more attentions due to the wider bandwidth and higher data rate that can meet the ever-increasing needs for multimedia, massive external data storage, or even biomedical applications. However, from manufacturing’s perspective, the circuits implementations are increasingly susceptible to fabrication process variations with the scaling of CMOS technology, which results in loss of yield rate. To solve this issue, a sensor-fusion solution is proposed in this paper by adding multiple on-chip sensors, including power detectors, temperature sensors, information envelope detectors and related filters, instrumentation amplifiers using a standard CMOS process. These sensors and detectors aim to collect critical system performance and environmental parameters, which will be utilized by a self-healing and optimization algorithm to adjust the state of system components by digitized control knobs.

scholarly journals Accurate Analysis and Design of Integrated Single Input Schmitt Trigger Circuits

2020 ◽  
Vol 10 (3) ◽  
pp. 21
Author(s):  
Mohamed R. Elmezayen ◽  
Wei Hu ◽  
Amr M. Maghraby ◽  
Islam T. Abougindia ◽  
Suat U. Ay
Keyword(s):  
Process Variations ◽  
Schmitt Trigger ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Original Design ◽  
Accurate Analysis ◽  
Single Input Single Output ◽  
Analysis And Design ◽  
Wide Range ◽  
Single Input

Schmitt trigger (ST) circuits are widely used integrated circuit (IC) blocks with hysteretic input/output (I/O) characteristics. Like the I/O characteristics of a living neuron, STs reject noise and provide stability to systems that they are deployed in. Indeed, single-input/single-output (SISO) STs are likely candidates to be the core unit element in artificial neural networks (ANNs) due not only to their similar I/O characteristics but also to their low power consumption and small silicon footprints. This paper presents an accurate and detailed analysis and design of six widely used complementary metal-oxide-semiconductor (CMOS) SISO ST circuits. The hysteresis characteristics of these ST circuits were derived for hand calculations and compared to original design equations and simulation results. Simulations were carried out in a well-established, 0.35 μm/3.3 V, analog/mixed-signal CMOS process. Additionally, simulations were performed using a wide range of supplies and process variations, but only 3.3 V supply results are presented. Most of the new design equations provide better accuracy and insights, as broad assumptions of original derivations were avoided.

scholarly journals Chaos-Based Physical Unclonable Functions

2019 ◽  
Vol 9 (5) ◽  
pp. 991 ◽  
Author(s):  
Krzysztof Gołofit ◽  
Piotr Wieczorek
Keyword(s):  
Current Trend ◽  
Process Variations ◽  
Continuous Variable ◽  
Chaotic Circuit ◽  
Physically Unclonable Functions ◽  
Cryptographic Keys ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Programmable Logic Devices ◽  
Placement And Routing

The concept presented in this paper fits into the current trend of highly secured hardware authentication designs utilizing Physically Unclonable Functions (PUFs) or Physical Obfuscated Keys (POKs). We propose an idea that the PUF cryptographic keys can be derived from a chaotic circuit. We point out that the chaos theory should be explored for the sake of PUFs as a natural mechanism of amplifying random process variations of digital circuits. We prove the idea based on a novel design of a chaotic circuit, which utilizes time in a feedback loop as an analog continuous variable in a purely digital system. Our design is small and simple, and therefore feasible to implement in inexpensive reprogrammable devices (not equipped with digital clock manager, programmable delay line, phase locked loop, RAM/ROM memory, etc.). Preliminary tests proved that the chaotic circuit PUFs work in both advanced Field-Programmable Gate Arrays (FPGAs) as well as simple Complex Programmable Logic Devices (CPLDs). We showed that different PUF challenges (slightly different implementations based on variations in elements placement and/or routing) have provided significantly different keys generated within one CPLD/FPGA device. On the other hand, the same PUF challenges used in a different CPLD/FPGA instance (programmed with precisely the same bit-stream resulting in exactly the same placement and routing) have enhanced differences between devices resulting in different cryptographic keys.

VOLTAGE DRIVEN NONDESTRUCTIVE SELF-REFERENCE SENSING FOR STT-RAM YIELD ENHANCEMENT

SPIN ◽  
2012 ◽  
Vol 02 (03) ◽  
pp. 1240008
Author(s):  
HAI (HELEN) LI ◽  
ZHENYU SUN
Keyword(s):  
Cell Structure ◽  
Random Access ◽  
Process Variations ◽  
Spin Transfer Torque ◽  
Yield Enhancement ◽  
Cmos Process ◽  
Standby Power ◽  
Magnetic Tunneling ◽  
Non Destructive ◽  
Self Reference

Spin-transfer torque random access memory (STT-RAM) has demonstrated great potentials as a universal memory for its fast access speed, zero standby power, excellent scalability and simplicity of cell structure. However, large process variations of both magnetic tunneling junction and CMOS process severely limit the yield of STT-RAM chips. In this paper, we propose a novel voltage-driven non-destructive self-reference sensing scheme (NDRS) to enhance the STT-RAM chip yield by significantly improving sense margin. Monte-Carlo simulations of a 16 Kb STT-RAM array shows that our proposed scheme can achieve the same yield as the previous NDRS scheme while improving the sense margin by 5 × with the similar access performance and power.

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