scholarly journals Chaos-Based Physical Unclonable Functions

2019 ◽  
Vol 9 (5) ◽  
pp. 991 ◽  
Author(s):  
Krzysztof Gołofit ◽  
Piotr Wieczorek
Keyword(s):  
Current Trend ◽  
Process Variations ◽  
Continuous Variable ◽  
Chaotic Circuit ◽  
Physically Unclonable Functions ◽  
Cryptographic Keys ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Programmable Logic Devices ◽  
Placement And Routing

The concept presented in this paper fits into the current trend of highly secured hardware authentication designs utilizing Physically Unclonable Functions (PUFs) or Physical Obfuscated Keys (POKs). We propose an idea that the PUF cryptographic keys can be derived from a chaotic circuit. We point out that the chaos theory should be explored for the sake of PUFs as a natural mechanism of amplifying random process variations of digital circuits. We prove the idea based on a novel design of a chaotic circuit, which utilizes time in a feedback loop as an analog continuous variable in a purely digital system. Our design is small and simple, and therefore feasible to implement in inexpensive reprogrammable devices (not equipped with digital clock manager, programmable delay line, phase locked loop, RAM/ROM memory, etc.). Preliminary tests proved that the chaotic circuit PUFs work in both advanced Field-Programmable Gate Arrays (FPGAs) as well as simple Complex Programmable Logic Devices (CPLDs). We showed that different PUF challenges (slightly different implementations based on variations in elements placement and/or routing) have provided significantly different keys generated within one CPLD/FPGA device. On the other hand, the same PUF challenges used in a different CPLD/FPGA instance (programmed with precisely the same bit-stream resulting in exactly the same placement and routing) have enhanced differences between devices resulting in different cryptographic keys.

scholarly journals Four-Step Current Commutation Strategy for a Matrix Converter Based on Enhanced-PWM MCU Peripherals

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 547 ◽  
Author(s):  
Luis Ramon Merchan-Villalba ◽  
Jose Merced Lozano-Garcia ◽  
Diego Armando de Jesus Gutierrez-Torres ◽  
Juan Gabriel Avina-Cervantes ◽  
Alejandro Pizano-Martinez
Keyword(s):  
Pulse Width Modulation ◽  
Matrix Converter ◽  
Programmable Logic ◽  
Gate Arrays ◽  
Field Programmable ◽  
Power Switches ◽  
Current Commutation ◽  
Programmable Gate Arrays ◽  
Programmable Logic Devices ◽  
Microcontroller Unit

In this paper, an efficient implementation of the four-step current commutation technique for controlling bidirectional power switches in a Matrix Converter (MC) is proposed. This strategy is based on the enhanced pulse width modulation peripheral included in the C 2000 Delfino 32-bit microcontroller of Texas Instruments. By tuning the algorithmic parameters contained in this module, the four-step commutation process is carried out on the Microcontroller Unit (MCU) without overloading the full complex processor and avoiding the use of additional special hardware such as Field-Programmable Gate Arrays (FPGA) or Complex Programmable Logic Devices (CPLD) when controlling the MC. The algorithm is implemented on the TMS320F28379D MCU and operationally validated on an MC prototype, where the functionality of the proposal is demonstrated.

scholarly journals Placement and Routing for Performance-Oriented FPGA Layout

VLSI Design ◽  
1998 ◽  
Vol 7 (1) ◽  
pp. 97-110 ◽  
Author(s):  
Michael J. Alexander ◽  
James P. Cohoon ◽  
Joseph L. Ganley ◽  
Gabriel Robins
Keyword(s):  
Field Programmable Gate Arrays ◽  
Channel Width ◽  
Global Routing ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Placement And Routing ◽  
Source Sink ◽  
Geometric Partitioning ◽  
Place And Route

This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graph-based strategy for detailed routing, our tool optimizes source-sink pathlengths, channel width and total wirelength. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel width required to place and route several benchmarks.

scholarly journals A New Arbiter PUF for Enhancing Unpredictability on FPGA

2015 ◽  
Vol 2015 ◽  
pp. 1-13 ◽  
Author(s):  
Takanori Machida ◽  
Dai Yamamoto ◽  
Mitsugu Iwamoto ◽  
Kazuo Sakiyama
Keyword(s):  
Machine Learning ◽  
Field Programmable Gate Arrays ◽  
Physically Unclonable Functions ◽  
Gate Arrays ◽  
Training Samples ◽  
Field Programmable ◽  
Arbiter Puf ◽  
Programmable Gate Arrays ◽  
Novel Design

In general, conventional Arbiter-based Physically Unclonable Functions (PUFs) generate responses with low unpredictability. TheN-XOR Arbiter PUF, proposed in 2007, is a well-known technique for improving this unpredictability. In this paper, we propose a novel design for Arbiter PUF, calledDouble Arbiter PUF, to enhance the unpredictability on field programmable gate arrays (FPGAs), and we compare our design to conventionalN-XOR Arbiter PUFs. One metric for judging the unpredictability of responses is to measure their tolerance to machine-learning attacks. Although our previous work showed the superiority of Double Arbiter PUFs regarding unpredictability, its details were not clarified. We evaluate the dependency on the number of training samples for machine learning, and we discuss the reason why Double Arbiter PUFs are more tolerant than theN-XOR Arbiter PUFs by evaluatingintrachip variation. Further, the conventional Arbiter PUFs and proposed Double Arbiter PUFs are evaluated according to other metrics, namely, their uniqueness, randomness, and steadiness. We demonstrate that3-1 Double Arbiter PUFarchives the best performance overall.

A novel approach to the placement and routing problems for field programmable gate arrays

2007 ◽  
Vol 7 (1) ◽  
pp. 455-470 ◽  
Author(s):  
Siva Nageswara Rao Borra ◽  
Annamalai Muthukaruppan ◽  
S. Suresh ◽  
V. Kamakoti
Keyword(s):  
Field Programmable Gate Arrays ◽  
Routing Problems ◽  
Gate Arrays ◽  
Novel Approach ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Placement And Routing

scholarly journals Power optimisation using intelligent Clock gating dedicated for block RAM cascading technique in FPGA design.

2021 ◽  
Author(s):  
gurwinder singh ◽  
Munish Rattan ◽  
Gurjot Kaur Walia
Keyword(s):  
Digital Circuits ◽  
Current Trend ◽  
Critical Energy ◽  
Clock Gating ◽  
Fpga Design ◽  
Gate Arrays ◽  
Field Programmable ◽  
Chip Size ◽  
Programmable Gate Arrays ◽  
High Level

Abstract The current trend is the combination of chip size reduction and an increase in the number of circuits on chips has provided significant growth in battery consumption and critical energy efficiency leading to growth in the emerging Low Power Electronics sector. Our paper is committed to optimizing the power by eliminating cascading in block RAM. It dominates the amount of power dissipated in SOCs (System on Chips). High-level integration (HLS) allows hardware designers to think logically and not worry about low-level, cyclical details. It arranges the capability to quickly access the slot of design and the tradeoff between resource utilization and operation. Field Programmable Gate Arrays (FP- GAs) show significant progress in measuring speed and capacity to create a platform for the use of digital circuits. In the design of the FPGA, integration tools are used that perform various mitigation and improvement strategies. Integration tools utilize the RTL representation of a project with time constraints and generate a network list of the same level. Today, the advanced Xilinx Vivado Design Suite is used for FPGA design as a blending tool. In some cases, the Xilinx Vivado is unable to meet the required designer delays and power constraints. Therefore the primary goal of this paper is to optimize the power in design constraints in the Xilinx Vivado software.

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