- Partially Reconfigurable Processor for Wireless Receiver Applications

Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping

2010 International Conference on Field-Programmable Technology ◽

10.1109/fpt.2010.5681431 ◽

2010 ◽

Cited By ~ 1

Author(s):

Kazuei Hironaka ◽

Masayuki Kimura ◽

Yoshiki Saito ◽

Toru Sano ◽

Masaru Kato ◽

...

Keyword(s):

Power Consumption ◽

Reducing Power ◽

Processor Array ◽

Reconfigurable Processor ◽

Dynamically Reconfigurable

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A 60-dB DR PGA with DC-offset calibration for short-distance wireless receiver

VLSI Design, Automation and Test(VLSI-DAT) ◽

10.1109/vlsi-dat.2015.7114572 ◽

2015 ◽

Cited By ~ 1

Author(s):

Xiaokun Zhao ◽

Zheng Song ◽

Baoyong Chi

Keyword(s):

Short Distance ◽

Wireless Receiver ◽

Dc Offset ◽

Dc Offset Calibration

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Real Time ELA De-Interlacing with the Xtensa Reconfigurable Processor

2006 IEEE North-East Workshop on Circuits and Systems ◽

10.1109/newcas.2006.250906 ◽

2006 ◽

Cited By ~ 1

Author(s):

Hossein Mohammadi ◽

Yvon Savaria ◽

J.M. Langlois

Keyword(s):

Real Time ◽

Reconfigurable Processor

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System analysis of a multi-standard direct conversion wireless receiver

The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002. ◽

10.1109/mwscas.2002.1187058 ◽

2003 ◽

Cited By ~ 3

Author(s):

A. Savla ◽

A. Ravindran ◽

J. Leonard ◽

M. Ismail

Keyword(s):

System Analysis ◽

Direct Conversion ◽

Wireless Receiver

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Chip-package-PCB co-design for optimization of wireless receiver performance

2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS) ◽

10.1109/edaps.2012.6469442 ◽

2012 ◽

Cited By ~ 1

Author(s):

Ruey-Bo Sun ◽

Po-Yang Chang ◽

Ting-Kuang Wang ◽

Chih-Ming Hung

Keyword(s):

Wireless Receiver ◽

Receiver Performance

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A data-flow graph generation algorithm for a coarse-grained reconfigurable processor

2009 IEEE 8th International Conference on ASIC ◽

10.1109/asicon.2009.5351548 ◽

2009 ◽

Author(s):

Chao Yang ◽

Shouyi Yin ◽

Leibo Liu ◽

Shaojun Wei

Keyword(s):

Data Flow ◽

Coarse Grained ◽

Data Flow Graph ◽

Flow Graph ◽

Generation Algorithm ◽

Reconfigurable Processor ◽

Graph Generation

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HIPERMA: A high performance and reconfigurable processor for SAR applications

2007 1st Asian and Pacific Conference on Synthetic Aperture Radar ◽

10.1109/apsar.2007.4418599 ◽

2007 ◽

Author(s):

Shushan Qiao ◽

Yong Hei ◽

Xinfeng Xu ◽

Bin Wu ◽

Yumei Zhou

Keyword(s):

High Performance ◽

Reconfigurable Processor

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Implementation of dynamically reconfigurable processor DAPDNA-2

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). ◽

10.1109/vdat.2005.1500086 ◽

2005 ◽

Cited By ~ 21

Author(s):

T. Sato ◽

H. Watanabe ◽

K. Shiba

Keyword(s):

Reconfigurable Processor ◽

Dynamically Reconfigurable

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An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor

Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005. ◽

10.1109/fpt.2005.1568541 ◽

2006 ◽

Cited By ~ 11

Author(s):

Y. Hasegawa ◽

S. Abe ◽

H. Matsutani ◽

H. Amano ◽

K. Anjo ◽

...

Keyword(s):

Reconfigurable Processor ◽

Dynamically Reconfigurable

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A 14-bit 500-MS/s SHA-less Pipelined ADC in 65nm CMOS Technology for Wireless Receiver

2018 IEEE 2nd International Conference on Circuits, System and Simulation (ICCSS) ◽

10.1109/cirsyssim.2018.8525871 ◽

2018 ◽

Author(s):

Yanhua Zhang ◽

Lijie Yang ◽

Ruirui Dang ◽

Zhiwei Xu ◽

Chunyi Song

Keyword(s):

Cmos Technology ◽

Pipelined Adc ◽

Wireless Receiver

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