The voltage-controlled low-pass filter based on FPGA frequency measurement

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 354 ◽  
Author(s):  
Huan Liu ◽  
Zhong Wu

A high-accuracy demodulation algorithm is required to estimate angular position and angular velocity from resolver signals. In order to improve the estimation accuracy of conventional phase-locked loop (PLL) based demodulation method, a Chebyshev filter-based type III PLL method is proposed in this paper. The proposed method makes PLL become a system of type III tracking loop, which could greatly reduce the theoretical constant deviation in the estimation results of conventional type II PLL in case of variable speed. Meanwhile, the eigenvalues of type III PLL are placed to be the same position as those of a Chebyshev low-pass filter. In this way, demodulation parameters with stronger filter properties can be obtained to effectively suppress the high-frequency measurement noise in resolver signals. Thus, the proposed method can achieve higher demodulation precision compared with the conventional ones. Simulations and experiments are performed to validate the proposed demodulation method.


Energies ◽  
2018 ◽  
Vol 11 (9) ◽  
pp. 2372 ◽  
Author(s):  
Sohail Khan ◽  
Benoit Bletterie ◽  
Adolfo Anta ◽  
Wolfgang Gawlik

This paper presents a methodology that aims at identifying virtual inertia (VI) gain limitations from virtual synchronous generators (VSGs) while maintaining the frequency stability considering the delay associated with the frequency measurement process. The phase-locked loop (PLL) is typically used for frequency estimation that is used to calculate the rate of change of frequency (RoCoF) and it drives the VI loop. The PLL is generally accompanied by a low-pass filter that aims to suppress the impact of harmonics. This filter introduces a delay that when used with the VI control loop causes stability issues for high values of VI gain. A comparison of various PLL approaches suggests that certain variants tend to permit higher value of cut-off frequencies which can be utilized to increase the VI gain limit from VSG. This study presents a method by which the upper limit on VI gain can be quantified and related to the cut-off frequency of the PLL low pass filter that is indirectly representing the delay. It is performed using small signal frequency stability analysis on the frequency domain model of the grid with virtual inertia emulating VSG. The effective maximum VI gain from VSG is explored while satisfying the frequency measurement accuracy specification considering harmonics. The results show that the requirements of reaching a stable operation with sufficient stability margins can still be met with a faster PLL-based system and the potential increases in VI support from VSG can be quantified using the proposed method. The study has been first performed on a single machine single inverter bus (SMSIB) system and is generalized to the multi-machine and multi-inverter system.


2017 ◽  
Vol E100.C (10) ◽  
pp. 858-865 ◽  
Author(s):  
Yohei MORISHITA ◽  
Koichi MIZUNO ◽  
Junji SATO ◽  
Koji TAKINAMI ◽  
Kazuaki TAKAHASHI

2016 ◽  
Vol 15 (12) ◽  
pp. 2579-2586
Author(s):  
Adina Racasan ◽  
Calin Munteanu ◽  
Vasile Topa ◽  
Claudia Pacurar ◽  
Claudia Hebedean

Author(s):  
Nanan Chomnak ◽  
Siradanai Srisamranrungrueang ◽  
Natapong Wongprommoon
Keyword(s):  

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