2006 ◽  
Vol 5 (1) ◽  
pp. 134-134
Author(s):  
L SCELSI ◽  
L TAVAZZI ◽  
A MAGGIONI ◽  
D LUCCI ◽  
G CACCIATORE ◽  
...  

2018 ◽  
Vol 18 (3) ◽  
pp. 250-259 ◽  
Author(s):  
Yangwoo Seo ◽  
Kyeshin Lee ◽  
Younho Lee ◽  
Jeyong Kim

Author(s):  
Rommel Estores ◽  
Pascal Vercruysse ◽  
Karl Villareal ◽  
Eric Barbian ◽  
Ralph Sanchez ◽  
...  

Abstract The failure analysis community working on highly integrated mixed signal circuitry is entering an era where simultaneously System-On-Chip technologies, denser metallization schemes, on-chip dissipation techniques and intelligent packages are being introduced. These innovations bring a great deal of defect accessibility challenges to the failure analyst. To contend in this era while aiming for higher efficiency and effectiveness, the failure analysis environment must undergo a disruptive evolution. The success or failure of an analysis will be determined by the careful selection of tools, data and techniques in the applied analysis flow. A comprehensive approach is required where hardware, software, data analysis, traditional FA techniques and expertise are complementary combined [1]. This document demonstrates this through the incorporation of advanced scan diagnosis methods in the overall analysis flow for digital functionality failures and supporting the enhanced failure analysis methodology. For the testing and diagnosis of the presented cases, compact but powerful scan test FA Lab hardware with its diagnosis software was used [2]. It can therefore easily be combined with the traditional FA techniques to provide stimulus for dynamic fault localizations [3]. The system combines scan chain information, failure data and layout information into one viewing environment which provides real analysis power for the failure analyst. Comprehensive data analysis is performed to identify failing cells/nets, provide a better overview of the failure and the interactions to isolate the fault further to a smaller area, or to analyze subtle behavior patterns to find and rationalize possible faults that are otherwise not detected. Three sample cases will be discussed in this document to demonstrate specific strengths and advantages of this enhanced FA methodology.


Author(s):  
Cheng-Piao Lin ◽  
Chin-Hsin Tang ◽  
Cheng-Hsu Wu ◽  
Cheng-Chun Ting

Abstract This paper analyzes several SRAM failures using nano-probing technique. Three SRAM single bit failures with different kinds of Gox breakdown defects analyzed are gross function single bit failure, data retention single bit failure, and special data retention single bit failure. The electrical characteristics of discrete 6T-SRAM cells with soft breakdown are discussed and correlated to evidences obtained from physical analysis. The paper also verifies many previously published simulation data. It utilizes a 6T-SRAM vehicle consisting of a large number of SRAM cells fabricated by deep sub-micron, dual gate, and copper metallization processes. The data obtained from this paper indicates that Gox breakdown location within NMOS pull-down device has larger a impact on SRAM stability than magnitude of gate leakage current, which agrees with previously published simulation data.


1991 ◽  
Vol 225 ◽  
Author(s):  
D. B. Knorr ◽  
K. P. Rodbell ◽  
D. P. Tracy

ABSTRACTPure aluminum films are deposited under a variety of conditions to vary the crystallographic texture. After patterning and annealing at 400°C for 1 hour, electromigration tests are performed at several temperatures. Failure data are compared on the basis of t50 and standard deviation. Microstructure is quantified by transmission electron microscopy for grain size and grain size distribution and by X-ray diffraction for texture. A strong (111) texture significantly improves the electromigration lifetime and decreases the standard deviation in time to failure. This improvement correlates with both the fraction and sharpness of the (111) texture component.


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