Verilog HDL Designs for Select Logic Functions

2009 ◽  
pp. 801-847
Keyword(s):  
Verilog Hdl ◽  
Logic Functions

High-Density Memristor-CMOS Ternary Logic Family

2020 ◽  
Author(s):  
Xiaoyuan Wang ◽  
Pengfei Zhou ◽  
Jason Eshraghian ◽  
Chih-Yang Lin ◽  
Herbert Ho-Ching Iu ◽  
...  
Keyword(s):  
Indium Tin Oxide ◽  
Practical Implementation ◽  
Switching Speed ◽  
High Data ◽  
Fast Switching ◽  
Data Density ◽  
Order Of Magnitude ◽  
High Transconductance ◽  
Logic Functions ◽  
Magnitude Improvement

<div>This paper presents the first experimental demonstration</div><div>of a ternary memristor-CMOS logic family. We systematically</div><div>design, simulate and experimentally verify the primitive</div><div>logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance.</div>

scholarly journals Decision Tree-Based Adaptive Reconfigurable Cache Scheme

Algorithms ◽  
2021 ◽  
Vol 14 (6) ◽  
pp. 176
Author(s):  
Wei Zhu ◽  
Xiaoyang Zeng
Keyword(s):  
Decision Tree ◽  
Adaptive Algorithms ◽  
Memory Access ◽  
Access Time ◽  
Decision Tree Algorithm ◽  
Verilog Hdl ◽  
Tree Model ◽  
Cache Associativity ◽  
Cache Scheme ◽  
Reconfigurable Cache

Applications have different preferences for caches, sometimes even within the different running phases. Caches with fixed parameters may compromise the performance of a system. To solve this problem, we propose a real-time adaptive reconfigurable cache based on the decision tree algorithm, which can optimize the average memory access time of cache without modifying the cache coherent protocol. By monitoring the application running state, the cache associativity is periodically tuned to the optimal cache associativity, which is determined by the decision tree model. This paper implements the proposed decision tree-based adaptive reconfigurable cache in the GEM5 simulator and designs the key modules using Verilog HDL. The simulation results show that the proposed decision tree-based adaptive reconfigurable cache reduces the average memory access time compared with other adaptive algorithms.

scholarly journals Skyrmion Logic-In-Memory Architecture for Maximum/Minimum Search

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 155
Author(s):  
Luca Gnoli ◽  
Fabrizio Riente ◽  
Marco Vacca ◽  
Massimo Ruo Roch ◽  
Mariagrazia Graziano
Keyword(s):  
High Efficiency ◽  
Digital Design ◽  
Control Logic ◽  
Minimum Number ◽  
Physical Simulations ◽  
Good Energy ◽  
Logic Functions ◽  
Time And Energy ◽  
Cmos Implementation ◽  
Maximum Minimum

In modern computing systems there is the need to utilize a large amount of data in maintaining high efficiency. Limited memory bandwidth, coupled with the performance gap between memory and logic, impacts heavily on algorithms performance, increasing the overall time and energy required for computation. A possible approach to overcome such limitations is Logic-In-Memory (LIM). In this paper, we propose a LIM architecture based on a non-volatile skyrmion-based recetrack memory. The architecture can be used as a memory or can perform advanced logic functions on the stored data, for example searching for the maximum/minimum number. The circuit has been designed and validated using physical simulations for the memory array together with digital design tools for the control logic. The results highlight the small area of the proposed architecture and its good energy efficiency compared with a reference CMOS implementation.

scholarly journals Training an asymmetric signal perceptron through reinforcement in an artificial chemistry

2014 ◽  
Vol 11 (93) ◽  
pp. 20131100 ◽  
Author(s):  
Peter Banda ◽  
Christof Teuscher ◽  
Darko Stefanovic
Keyword(s):  
State Of The Art ◽  
Chemical Species ◽  
Mass Action ◽  
Mass Action Kinetics ◽  
Dna Strand Displacement ◽  
Autonomous Adaptation ◽  
Biochemical Systems ◽  
Dna Strand ◽  
Logic Functions ◽  
Application Specific

State-of-the-art biochemical systems for medical applications and chemical computing are application-specific and cannot be reprogrammed or trained once fabricated. The implementation of adaptive biochemical systems that would offer flexibility through programmability and autonomous adaptation faces major challenges because of the large number of required chemical species as well as the timing-sensitive feedback loops required for learning. In this paper, we begin addressing these challenges with a novel chemical perceptron that can solve all 14 linearly separable logic functions. The system performs asymmetric chemical arithmetic, learns through reinforcement and supports both Michaelis–Menten as well as mass-action kinetics. To enable cascading of the chemical perceptrons, we introduce thresholds that amplify the outputs. The simplicity of our model makes an actual wet implementation, in particular by DNA-strand displacement, possible.

Programming Cell Adhesion for On-Chip Sequential Boolean Logic Functions

2017 ◽  
Vol 139 (30) ◽  
pp. 10176-10179 ◽  
Author(s):  
Xiangmeng Qu ◽  
Shaopeng Wang ◽  
Zhilei Ge ◽  
Jianbang Wang ◽  
Guangbao Yao ◽  
...  
Keyword(s):  
Cell Adhesion ◽  
Boolean Logic ◽  
On Chip ◽  
Logic Functions
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