DSP System Level Concepts and Digital Filter Implementations

A Two-Level Task Scheduler on Multiple DSP System for OpenCL

Advances in Mechanical Engineering ◽

10.1155/2014/754835 ◽

2014 ◽

Vol 6 ◽

pp. 754835

Author(s):

Li Tian ◽

Cai Meng ◽

Fugen Zhou

Keyword(s):

Dynamic Loading ◽

Task Switching ◽

Experimental Results ◽

System Level ◽

Synchronization Mechanism ◽

Schedule System ◽

Multiple Cores ◽

Dsp System ◽

Dsp Systems ◽

Work Item

This paper addresses the problem that multiple DSP system does not support OpenCL programming. With the compiler, runtime, and the kernel scheduler proposed, an OpenCL application becomes portable not only between multiple CPU and GPU, but also between embedded multiple DSP systems. Firstly, the LLVM compiler was imported for source-to-source translation in which the translated source was supported by CCS. Secondly, two-level schedulers were proposed to support efficient OpenCL kernel execution. The DSP/BIOS is used to schedule system level tasks such as interrupts and drivers; however, the synchronization mechanism resulted in heavy overhead during task switching. So we designed an efficient second level scheduler especially for OpenCL kernel work-item scheduling. The context switch process utilizes the 8 functional units and cross path links which was superior to DSP/BIOS in the aspect of task switching. Finally, dynamic loading and software managed CACHE were redesigned for OpenCL running on multiple DSP system. We evaluated the performance using some common OpenCL kernels from NVIDIA, AMD, NAS, and Parboil benchmarks. Experimental results show that the DSP OpenCL can efficiently exploit the computing resource of multiple cores.

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Coverage Directed Generation of System-Level Test Cases for the Validation of a DSP System

Lecture Notes in Computer Science - FME 2001: Formal Methods for Increasing Software Productivity ◽

10.1007/3-540-45251-6_26 ◽

2001 ◽

pp. 449-464 ◽

Cited By ~ 2

Author(s):

Laurent Arditi ◽

Hédi Boufaïed ◽

Arnaud Cavanié ◽

Vincent Stehlé

Keyword(s):

System Level ◽

Test Cases ◽

Dsp System

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Application of evolutionary algorithm to design minimal phase digital filters with non-standard amplitude characteristics and finite bit word length

Bulletin of the Polish Academy of Sciences Technical Sciences ◽

10.2478/v10175-011-0016-z ◽

2011 ◽

Vol 59 (2) ◽

pp. 125-135 ◽

Cited By ~ 4

Author(s):

A. Słowik

Keyword(s):

Evolutionary Algorithm ◽

Digital Filter ◽

Word Length ◽

Digital Filters ◽

Infinite Impulse Response ◽

Mutation Operator ◽

Mutation Operators ◽

Dsp System ◽

Minimal Phase ◽

Amplitude Characteristics

Application of evolutionary algorithm to design minimal phase digital filters with non-standard amplitude characteristics and finite bit word length In this paper an application of evolutionary algorithm to design minimal phase digital filters with non-standard amplitude characteristics and with finite bit word length is presented. Four digital filters with infinite impulse response were designed using the proposed method. These digital filters possess: linearly falling characteristics, linearly growing characteristics, nonlinearly falling characteristics, and nonlinearly growing characteristics, and they are designed using bit words with an assumed length. This bit word length is connected with a processing register size. This register size depends on hardware possibilities where digital filter is to be implemented. In this paper, a modification of the mutation operator is introduced too. Due to this modification, better results were obtained in relation to the results obtained using the evolutionary algorithm with other mutation operators. The digital filters designed using the proposed method can be directly implemented in the hardware (DSP system) without any additional modifications.

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Low Power Adder Based Digital Filter for QRS Detector

The Scientific World JOURNAL ◽

10.1155/2014/405893 ◽

2014 ◽

Vol 2014 ◽

pp. 1-5

Author(s):

L. Murali ◽

D. Chitra ◽

T. Manigandan

Keyword(s):

Power Consumption ◽

Low Power ◽

Digital Filter ◽

Full Adder ◽

Leakage Power ◽

System Level ◽

Complex Signal ◽

Verilog Hdl ◽

Processing Elements ◽

Signal Processors

Most of the Biomedical applications use dedicated processors for the implementation of complex signal processing. Among them, sensor network is also a type, which has the constraint of low power consumption. Since the processing elements are the most copiously used operations in the signal processors, the power consumption of this has the major impact on the system level application. In this paper, we introduce low power concept of transistor stacking to reduce leakage power; and new architectures based on stacking to implement the full adder and its significance at the digital filter level for QRS detector are implemented. The proposed concept has lesser leakage power at the adder as well as filter level with trade-off in other quality metrics of the design. This enabled the design to be dealt with as the low-power corner and can be made adaptable to any level of hierarchical abstractions as per the requirement of the application. The proposed architectures are designed, modeled at RTL level using the Verilog-HDL, and synthesized in Synopsys Design Compiler by mapping the design to 65 nm technology library standard cells.

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