Hamming Codes

2017 ◽  
pp. 100-119
Keyword(s):  
Hamming Codes

scholarly journals Hamming Codes: Error Reducing Techniques

2021 ◽  
Vol 9 (11) ◽  
pp. 1972-1974
Author(s):  
Rohitkumar R Upadhyay
Keyword(s):  
Lower Bound ◽  
Error Correction ◽  
Coding Theory ◽  
Hamming Distance ◽  
Error Reduction ◽  
Error Correcting Codes ◽  
Significant Other ◽  
Hamming Codes ◽  
Decoding Algorithms ◽  
Reducing Properties

Abstract: Hamming codes for all intents and purposes are the first nontrivial family of error-correcting codes that can actually correct one error in a block of binary symbols, which literally is fairly significant. In this paper we definitely extend the notion of error correction to error-reduction and particularly present particularly several decoding methods with the particularly goal of improving the error-reducing capabilities of Hamming codes, which is quite significant. First, the error-reducing properties of Hamming codes with pretty standard decoding definitely are demonstrated and explored. We show a sort of lower bound on the definitely average number of errors present in a decoded message when two errors for the most part are introduced by the channel for for all intents and purposes general Hamming codes, which actually is quite significant. Other decoding algorithms are investigated experimentally, and it generally is definitely found that these algorithms for the most part improve the error reduction capabilities of Hamming codes beyond the aforementioned lower bound of for all intents and purposes standard decoding. Keywords: coding theory, hamming codes, hamming distance

scholarly journals Small weight bases for hamming codes

1995 ◽  
pp. 235-243
Author(s):  
John Tromp ◽  
Louxin Zhang ◽  
Ying Zhao
Keyword(s):  
Small Weight ◽  
Hamming Codes

Hamming-Codes und erweiterte Hamming-Codes

2003 ◽  
pp. 112-116
Author(s):  
Ralph-Hardo Schulz
Keyword(s):  
Hamming Codes

scholarly journals A Single Error Correcting Code with One-Step Group Partitioned Decoding Based on Shared Majority-Vote

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 709
Author(s):  
Abhishek Das ◽  
Nur A. Touba
Keyword(s):  
Optimization Technique ◽  
Error Correcting Code ◽  
Latin Square ◽  
Error Correcting Codes ◽  
Trade Off ◽  
Cache Memories ◽  
Hamming Codes ◽  
Single Error ◽  
Memory Overhead ◽  
On Chip

Technology scaling has led to an increase in density and capacity of on-chip caches. This has enabled higher throughput by enabling more low latency memory transfers. With the reduction in size of SRAMs and development of emerging technologies, e.g., STT-MRAM, for on-chip cache memories, reliability of such memories becomes a major concern. Traditional error correcting codes, e.g., Hamming codes and orthogonal Latin square codes, either suffer from high decoding latency, which leads to lower overall throughput, or high memory overhead. In this paper, a new single error correcting code based on a shared majority voting logic is presented. The proposed codes trade off decoding latency in order to improve the memory overhead posed by orthogonal Latin square codes. A latency optimization technique is also proposed which lowers the decoding latency by incurring a slight memory overhead. It is shown that the proposed codes achieve better redundancy compared to orthogonal Latin square codes. The proposed codes are also shown to achieve lower decoding latency compared to Hamming codes. Thus, the proposed codes achieve a balanced trade-off between memory overhead and decoding latency, which makes them highly suitable for on-chip cache memories which have stringent throughput and memory overhead constraints.

scholarly journals Error Detection and Correction On-Board Nanosatellites Using Hamming Codes

2019 ◽  
Vol 2019 ◽  
pp. 1-15 ◽  
Author(s):  
Caleb Hillier ◽  
Vipin Balyan
Keyword(s):  
Error Correction ◽  
Error Detection ◽  
Simulation Software ◽  
Hamming Code ◽  
Single Event ◽  
Hamming Codes ◽  
Single Event Effects ◽  
Effective Version ◽  
Fast Speed ◽  
Error Detection And Correction

The field of nanosatellites is constantly evolving and growing at a very fast speed. This creates a growing demand for more advanced and reliable EDAC systems that are capable of protecting all memory aspects of satellites. The Hamming code was identified as a suitable EDAC scheme for the prevention of single event effects on-board a nanosatellite in LEO. In this paper, three variations of Hamming codes are tested both in Matlab and VHDL. The most effective version was Hamming [16, 11, 4]2. This code guarantees single-error correction and double-error detection. All developed Hamming codes are suited for FPGA implementation, for which they are tested thoroughly using simulation software and optimized.

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