A New Structure for Random Access Memory Using Quantum-Dot Cellular Automata

2019 ◽  
Vol 17 (8) ◽  
pp. 595-600 ◽  
Author(s):  
Md. Abdullah-Al-Shafi ◽  
Ali Newaz Bahar
2019 ◽  
Vol 21 ◽  
pp. 100252 ◽  
Author(s):  
Azath Mubarakali ◽  
Jayabrabu Ramakrishnan ◽  
Dinesh Mavaluru ◽  
Amria Elsir ◽  
Omer Elsier ◽  
...  

2020 ◽  
Vol 29 (01n04) ◽  
pp. 2040010
Author(s):  
R. H. Gudlavalleti ◽  
B. Saman ◽  
R. Mays ◽  
Evan Heller ◽  
J. Chandy ◽  
...  

This paper presents the peripheral circuitry for a multivalued static random-access memory (SRAM) based on 2-bit CMOS cross-coupled inverters using spatial wavefunction switched (SWS) field effect transistors (SWSFETs). The novel feature is a two quantum well/quantum dot channel n-SWSFET access transistor. The reduction in area with four-bit storage-per-cell increases the memory density and efficiency of the SRAM array. The SWSFET has vertically stacked two-quantum well/quantum dot channels between the source and drain regions. The upper or lower quantum charge locations in the channel region is based on the input gate voltage. The analog behavioral modeling (ABM) of the SWSFET device is done using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit simulations for the proposed memory cell and addressing/peripheral circuitry are presented.


2017 ◽  
Vol 26 (12) ◽  
pp. 1730004 ◽  
Author(s):  
Sonia Afrooz ◽  
Nima Jafari Navimipour

Quantum-dot cellular automata (QCA) has come out as one of the potential computational structures for the emerging nanocomputing systems. It has a large capacity in the development of circuits with high space density and dissipation of low heat and allows faster computers to develop with lower power consumption. The QCA is a new appliance to realize nanolevel digital devices and study and analyze their various parameters. It is also a potential technology for low force and high-density memory plans. Large memory designs in QCA show unique features because of their architectural structure. In QCA-based architectures, memory must be maintained in motion, i.e., the memory state has to be continuously moved through a set of QCA cells. These architectures have different features, such as the number of bits stored in a loop, access type (serial or parallel) and cell arrangement for the memory bank. However, the decisive features of the QCA memory cell design are the number of cells, to put off the use of energy. Although the review and study of the QCA-based memories are very important, there is no complete and systematic literature review about the systematical analyses of the state of the mechanisms in this field. Therefore, there are five main types to provide systematic reviews about the QCA-based memories; including read only memory (ROM), register, flip-flop, content addressable memory (CAM) and random access memory (RAM). Also, it has provided the advantages and disadvantages of the reviewed mechanisms and their important challenges so that some interesting lines for any coming research are provided.


2020 ◽  
Vol 8 (42) ◽  
pp. 14789-14795
Author(s):  
Ya Lin ◽  
Xue Zhang ◽  
Xuanyu Shan ◽  
Tao Zeng ◽  
Xiaoning Zhao ◽  
...  

A photo-tunable and flexible organic RRAM device based on poly(4-vinylphenol) (PVP) and N-doped carbon quantum dot nanocomposites for encrypted image storage.


2017 ◽  
Vol 26 (03) ◽  
pp. 1740014
Author(s):  
Murali Lingalugari ◽  
Pik-Yiu Chan ◽  
John Chandy ◽  
Evan Heller ◽  
Faquir Jain

This paper presents a quantum dot access channel nonvolatile random access memory (QDAC-NVRAM) which has comparable write and erase times to conventional random access memories but consumes less power and has a smaller footprint. We have fabricated long-channel (W/L=15μm/10μm) nonvolatile random access memories (NVRAMs) with 4μs erase times. These devices are CMOS-compatible and employ novel quantum dot access channel (QDAC) which enables fast storage and retrieval of charge from the floating gate layer. In addition, QDNVRAMs are shown to be capable of storing multiple-bits and potentially scalable to sub 22nm. We are also presenting the simulation results. This paper also presents a memory array architecture using QDAC-NVRAMs.


2019 ◽  
Vol 28 (03n04) ◽  
pp. 1940018
Author(s):  
F. Jain ◽  
R. H. Gudlavalleti ◽  
R. Mays ◽  
B. Saman ◽  
P-Y. Chan ◽  
...  

Compared to multi-valued logic (MVL) with conventional 2-state FETs with a single threshold, MVL computing architectures, based on 4-state SWS (Spatial wavefunction switched) and QDG (quantum dot gate)-FETs having multiple thresholds, results in reduced device count, higher clock (CLK) speed, and lower power consumption. We have experimentally shown multi-state characteristics in SWS-FETs as well as QDG-FETs. This paper presents a novel QDG-SWS-FET that: (1) functions as a multi-bit FET for efficient low-power logic, (2) can be configured as a quantum dot (QD) nonvolatile random access memory (NVRAM), and (3) is suitable for in-memory MVL computing architecture that are compatible with sub-7nm technology nodes. A QDG-SWS-FET with the addition of a control gate dielectric layer functions as a NVRAM cell. Furthermore, it is shown that one single SWS-QD-NVRAM cell gives the functionality of a 1-bit NAND. We have developed circuit/device models and performed quantum simulations for novel multi-layer quantum dot/quantum well FETs and NVRAMs. Our simulations have shown 4-states/2-bit output-input transfer characteristics in SWS-CMOS inverters and NAND gates using two Si/SiGe quantum well channels.


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