A novel multiplexer-based structure for random access memory cell in quantum-dot cellular automata

2017 ◽  
Vol 521 ◽  
pp. 162-167 ◽  
Author(s):  
Mazaher Naji Asfestani ◽  
Saeed Rasouli Heikalabad
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Access Memory ◽  
Quantum Dot Cellular Automata

A new efficient design for random access memory based on quantum dot cellular automata nanotechnology

2019 ◽  
Vol 21 ◽  
pp. 100252 ◽  
Author(s):  
Azath Mubarakali ◽  
Jayabrabu Ramakrishnan ◽  
Dinesh Mavaluru ◽  
Amria Elsir ◽  
Omer Elsier ◽  
...  
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Random Access ◽  
Random Access Memory ◽  
Efficient Design ◽  
Access Memory ◽  
Quantum Dot Cellular Automata

A Novel Peripheral Circuit for SWSFET Based Multivalued Static Random-Access Memory

2020 ◽  
Vol 29 (01n04) ◽  
pp. 2040010
Author(s):  
R. H. Gudlavalleti ◽  
B. Saman ◽  
R. Mays ◽  
Evan Heller ◽  
J. Chandy ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Quantum Well ◽  
Field Effect Transistors ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Input Gate ◽  
Reduction In Area

This paper presents the peripheral circuitry for a multivalued static random-access memory (SRAM) based on 2-bit CMOS cross-coupled inverters using spatial wavefunction switched (SWS) field effect transistors (SWSFETs). The novel feature is a two quantum well/quantum dot channel n-SWSFET access transistor. The reduction in area with four-bit storage-per-cell increases the memory density and efficiency of the SRAM array. The SWSFET has vertically stacked two-quantum well/quantum dot channels between the source and drain regions. The upper or lower quantum charge locations in the channel region is based on the input gate voltage. The analog behavioral modeling (ABM) of the SWSFET device is done using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit simulations for the proposed memory cell and addressing/peripheral circuitry are presented.

Memory Designing Using Quantum-Dot Cellular Automata: Systematic Literature Review, Classification and Current Trends

2017 ◽  
Vol 26 (12) ◽  
pp. 1730004 ◽  
Author(s):  
Sonia Afrooz ◽  
Nima Jafari Navimipour
Keyword(s):  
Cellular Automata ◽  
Literature Review ◽  
Quantum Dot ◽  
Systematic Literature Review ◽  
Random Access ◽  
Memory Cell ◽  
Memory State ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Advantages And Disadvantages

Quantum-dot cellular automata (QCA) has come out as one of the potential computational structures for the emerging nanocomputing systems. It has a large capacity in the development of circuits with high space density and dissipation of low heat and allows faster computers to develop with lower power consumption. The QCA is a new appliance to realize nanolevel digital devices and study and analyze their various parameters. It is also a potential technology for low force and high-density memory plans. Large memory designs in QCA show unique features because of their architectural structure. In QCA-based architectures, memory must be maintained in motion, i.e., the memory state has to be continuously moved through a set of QCA cells. These architectures have different features, such as the number of bits stored in a loop, access type (serial or parallel) and cell arrangement for the memory bank. However, the decisive features of the QCA memory cell design are the number of cells, to put off the use of energy. Although the review and study of the QCA-based memories are very important, there is no complete and systematic literature review about the systematical analyses of the state of the mechanisms in this field. Therefore, there are five main types to provide systematic reviews about the QCA-based memories; including read only memory (ROM), register, flip-flop, content addressable memory (CAM) and random access memory (RAM). Also, it has provided the advantages and disadvantages of the reviewed mechanisms and their important challenges so that some interesting lines for any coming research are provided.

Quantum Dot Floating Gate Nonvolatile Random Access Memory Using Ge Quantum Dot Channel for Faster Erasing

2018 ◽  
Vol 27 (01n02) ◽  
pp. 1840006
Author(s):  
Murali Lingalugari ◽  
Evan Heller ◽  
Barath Parthasarathy ◽  
John Chandy ◽  
Faquir Jain
Keyword(s):  
Quantum Dot ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Floating Gate ◽  
Access Memory ◽  
Access Channel ◽  
Ge Quantum Dot ◽  
Long Channel ◽  
Lower Voltage

This paper presents an approach to enhance floating gate quantum dot nonvolatile random access memory (QDNVRAM) cells in terms of higher-speed and lower-voltage Erase not possible with conventional floating gate nonvolatile memories. It is achieved by directly accessing the floating gate layer with a Ge quantum dot access channel via an additional drain (D2) during the Erase and/or Write operation. Quantum mechanical simulations in GeOx-cladded Ge quantum dot layers functioning as the floating gate as well access channel to facilitate Erase and Write are presented. Experimental data on fabricated long channel nonvolatile random access memory cell with SiOx-cladded Si dots is presented. Quantum simulations show lower voltage operation for GeOx-cladded Ge QD floating gate than SiOx-cladded Si dots. The Erase time is orders of magnitude faster than flash and is comparable to competing NVRAMs.

scholarly journals Pre-Emphasis Pulse Design for Random-Access Memory

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1454
Author(s):  
Yoshihiro Sugiura ◽  
Toru Tanzawa
Keyword(s):  
Time Constant ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Memory Access ◽  
Access Time ◽  
Access Memory ◽  
Delay Times ◽  
Cell Current ◽  
The Impact

This paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact of the process variation in the time constant of WL, the cell current, and the resistance of deciding path on optimum PE pulses are discussed. Optimum PE pulse widths and resultant minimum WL delay times are modeled with fitting curves as a function of column address of the accessed memory cell, which provides designers with the ability to set the optimum timing for WL and BL (bit-line) operations, reducing average memory access time.

Sign in / Sign up

Export Citation Format

Share Document