D.C. Performance Analysis of High-K Adiabatic Logic Circuits in Sub-Threshold Regime for RF Applications

Savio Jay Sengupta; Dipanjan Sen; Swarnil Roy; Manash Chanda; Subir Kumar Sarkar

doi:10.1166/sl.2019.4102

D.C. Performance Analysis of High-K Adiabatic Logic Circuits in Sub-Threshold Regime for RF Applications

Sensor Letters ◽

10.1166/sl.2019.4102 ◽

2019 ◽

Vol 17 (6) ◽

pp. 487-496 ◽

Cited By ~ 1

Author(s):

Savio Jay Sengupta ◽

Dipanjan Sen ◽

Swarnil Roy ◽

Manash Chanda ◽

Subir Kumar Sarkar

Keyword(s):

Performance Analysis ◽

Logic Circuits ◽

High K ◽

Adiabatic Logic ◽

Rf Applications ◽

Threshold Regime

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Effect of High-K Dielectric on the Performances of Adiabatic Logic Circuits in Sub-Threshold Regime

2018 IEEE Electron Devices Kolkata Conference (EDKCON) ◽

10.1109/edkcon.2018.8770492 ◽

2018 ◽

Author(s):

Savio Jay Sengupta ◽

Samarthi Chakraborty ◽

Tamal Sarkar ◽

Md. Zishan Iqbal ◽

Manash Chanda

Keyword(s):

Logic Circuits ◽

High K ◽

Adiabatic Logic ◽

High K Dielectric ◽

Threshold Regime

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Performance Analysis of 2N-N-2P Adiabatic Logic Circuits for Low Power Applications using FinFET

Procedia Computer Science ◽

10.1016/j.procs.2017.09.122 ◽

2017 ◽

Vol 115 ◽

pp. 166-173 ◽

Cited By ~ 3

Author(s):

B.P. Bhuvana ◽

V.S. Kanchana Bhaaskaran

Keyword(s):

Performance Analysis ◽

Low Power ◽

Logic Circuits ◽

Adiabatic Logic

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Performance Analysis of Adder Architecture using Modified Pass transistor Adiabatic Logic Circuits

2019 International Conference on Smart Systems and Inventive Technology (ICSSIT) ◽

10.1109/icssit46314.2019.8987840 ◽

2019 ◽

Author(s):

B P Bhuvana ◽

V S Kanchana Bhaaskaran

Keyword(s):

Performance Analysis ◽

Logic Circuits ◽

Adiabatic Logic ◽

Pass Transistor

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Designs and Implementations of Energy-Efficient Single-Phase Clock Pass Transistor Adiabatic Logic Circuits

Recent Patents on Electrical & Electronic Engineering e ◽

10.2174/22131116113066660009 ◽

2013 ◽

Vol 6 (3) ◽

pp. 173-182

Author(s):

Yanfei Zhang ◽

Jianping Hu

Keyword(s):

Energy Efficient ◽

Single Phase ◽

Logic Circuits ◽

Adiabatic Logic ◽

Pass Transistor ◽

Phase Clock

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High-K gate dielectric depletion-mode and enhancement-mode GaN MOS-HEMTs for improved OFF-state leakage and DIBL for power electronics and RF applications

2015 IEEE International Electron Devices Meeting (IEDM) ◽

10.1109/iedm.2015.7409710 ◽

2015 ◽

Cited By ~ 2

Author(s):

H. W. Then ◽

L. A. Chow ◽

S. Dasgupta ◽

S. Gardner ◽

M. Radosavljevic ◽

...

Keyword(s):

Power Electronics ◽

Gate Dielectric ◽

Enhancement Mode ◽

High K ◽

Rf Applications ◽

High K Gate Dielectric

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The Ramped-step Voltage in Adiabatic Logic Circuits: Analysis of Parameters to Further Reduce Power Dissipation

Research Journal of Applied Sciences Engineering and Technology ◽

10.19026/rjaset.5.5092 ◽

2013 ◽

Vol 5 (1) ◽

pp. 114-117

Author(s):

Nazrul Anuar Nayan ◽

Yasuhiro Takahashi ◽

Toshikazu Sekine

Keyword(s):

Power Dissipation ◽

Logic Circuits ◽

Step Voltage ◽

Adiabatic Logic

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A Survey on Adiabatic Logic Families for Implementing Reversible Logic Circuits

2018 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC) ◽

10.1109/iccic.2018.8782347 ◽

2018 ◽

Author(s):

R. M Bommi ◽

Raja S Selvakumar

Keyword(s):

Logic Circuits ◽

Reversible Logic ◽

Adiabatic Logic

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Performance analysis of sampling switch structures for wideband sigma-delta noise shapers for RF applications

ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549) ◽

10.1109/icasic.2001.982537 ◽

2002 ◽

Cited By ~ 4

Author(s):

A. Gothenberg ◽

H. Tenhunen

Keyword(s):

Performance Analysis ◽

Sigma Delta ◽

Rf Applications ◽

Noise Shapers

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Performance analysis of long Ge channel double gate (DG) p MOSFETs with high-k gate dielectrics based on carrier concentration formulation

Microelectronics Reliability ◽

10.1016/j.microrel.2011.02.004 ◽

2011 ◽

Vol 51 (6) ◽

pp. 1105-1112 ◽

Cited By ~ 6

Author(s):

Swagata Bhattacherjee ◽

Abhijit Biswas

Keyword(s):

Performance Analysis ◽

Carrier Concentration ◽

Gate Dielectrics ◽

Double Gate ◽

High K

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Power-Clock Gating in Adiabatic Logic Circuits

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/11556930_65 ◽

2005 ◽

pp. 638-646 ◽

Cited By ~ 12

Author(s):

Philip Teichmann ◽

Jürgen Fischer ◽

Stephan Henzler ◽

Ettore Amirante ◽

Doris Schmitt-Landsiedel

Keyword(s):

Logic Circuits ◽

Clock Gating ◽

Adiabatic Logic

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