Sub-100-nA-Operating Si-Compatible Ni/Ti/HfO2/SiO2/Si RRAM Device for High-Density Integration and Low-Power Applications

2016 ◽  
Vol 16 (10) ◽  
pp. 10247-10251 ◽  
Author(s):  
Sungjun Kim ◽  
Seongjae Cho ◽  
Byung-Gook Park
Keyword(s):  
Low Power ◽  
High Density

Design of Distributed Electrode Switching Device for High Density Resistivity Instrument

2014 ◽  
Vol 971-973 ◽  
pp. 436-439
Author(s):  
Jun Wei Shi ◽  
Ting Zhe Huang ◽  
Lei Zhang ◽  
Ying Jie Han ◽  
Da Wu ◽  
...  
Keyword(s):  
Low Power ◽  
Software Design ◽  
Design Method ◽  
Field Work ◽  
High Density ◽  
Switching Device ◽  
Switching Circuits

Distributed electrode switching device is an important part of high density resistivity instrument, and its performance will directly affect the usage of high density resistivity instrument in field work. This thesis introduces a design method of distributed electrode switching device. The device utilizes MCU to control magnetic latching relays to switch, and thus controls electrodes to switch automatically. It also utilizes RS485 chips to complete communication with adjoining electrode switching circuits. In order to test the device, this thesis introduces a software design method and the device turns out to be low power, small size and high reliable.

3D Integration of Wide IO Memory Cube Stacking to 28 nm Logic Chip with High Density TSV through a Fabless Supplier Chain

2012 ◽  
Vol 2012 (1) ◽  
pp. 000018-000022
Author(s):  
S.Q. Gu ◽  
D.W. King ◽  
V. Ramachandran ◽  
B. Henderson ◽  
U. Ray ◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Density ◽  
Temperature Cycle ◽  
Large Bandwidth ◽  
Supplier Chain ◽  
Chip Fabrication ◽  
Logic Process ◽  
Detrimental Impact ◽  
28 Nm

Wide IO memory has higher IO–count (up to 16×) than typical low power DDR memory, which could enable higher system bandwidth at low power. Wide IO DRAM can be stacked as Micro Pillar Grid Array (MPGA) cubes [1], which will provide high memory density for the system. With the high number (∼1200) of connections to the MPGA, a direct face to back stack (3D) to logic chip with high density TSV is the most efficient approach. To utilize the extra large bandwidth, the logic chip containing high speed processors requires logic chip fabrication in advanced node devices. In this paper, we report the–demonstration of a 2-memory chip JEDEC standard wide IO MPGA stacking on logic chip through a fabless supplier chain. A successful integration of via middle through Si via (TSV) to 28 nm logic process has been demonstrated with minimum impact to logic devices. The final package showed good TSV and ubump integrity. The wide IO memory is functional post stacking. In addition, the early reliability data for TSV and ubump showed no detrimental impact through temperature cycle and high temperature storage.

scholarly journals Low Power Consumption Nanofilamentary ECM and VCM Cells in a Single Sidewall of High‐Density VRRAM Arrays

2019 ◽  
Vol 6 (24) ◽  
pp. 1902363 ◽  
Author(s):  
Min‐Ci Wu ◽  
Yi‐Hsin Ting ◽  
Jui‐Yuan Chen ◽  
Wen‐Wei Wu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Density ◽  
Low Power Consumption
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