Characterization and analysis of graded index optical waveguides for the realization of low-power, high-density, and high-speed optical link

2012 ◽  
Author(s):  
Hsiang-Han Hsu ◽  
Takaaki Ishigure ◽  
Shigeru Nakagawa
2012 ◽  
Vol 2012 (1) ◽  
pp. 000018-000022
Author(s):  
S.Q. Gu ◽  
D.W. King ◽  
V. Ramachandran ◽  
B. Henderson ◽  
U. Ray ◽  
...  

Wide IO memory has higher IO–count (up to 16×) than typical low power DDR memory, which could enable higher system bandwidth at low power. Wide IO DRAM can be stacked as Micro Pillar Grid Array (MPGA) cubes [1], which will provide high memory density for the system. With the high number (∼1200) of connections to the MPGA, a direct face to back stack (3D) to logic chip with high density TSV is the most efficient approach. To utilize the extra large bandwidth, the logic chip containing high speed processors requires logic chip fabrication in advanced node devices. In this paper, we report the–demonstration of a 2-memory chip JEDEC standard wide IO MPGA stacking on logic chip through a fabless supplier chain. A successful integration of via middle through Si via (TSV) to 28 nm logic process has been demonstrated with minimum impact to logic devices. The final package showed good TSV and ubump integrity. The wide IO memory is functional post stacking. In addition, the early reliability data for TSV and ubump showed no detrimental impact through temperature cycle and high temperature storage.


2007 ◽  
Vol 127 (10) ◽  
pp. 1033-1042
Author(s):  
Tamio Okutani ◽  
Nobuyuki Nakamura ◽  
Hisato Araki ◽  
Shouji Irie ◽  
Hiroki Osa ◽  
...  
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