Impact of Random Dopant Fluctuation Effect on Surrounding Gate MOSFETs: From Atomic Level Simulation to Circuit Performance Evaluation

2011 ◽  
Vol 11 (12) ◽  
pp. 10429-10432 ◽  
Author(s):  
Hao Wang ◽  
Chenyue Ma ◽  
Chenfei Zhang ◽  
Jin He ◽  
Zhiwei Liu ◽  
...  
Keyword(s):  
Performance Evaluation ◽  
Atomic Level ◽  
Fluctuation Effect ◽  
Circuit Performance ◽  
Random Dopant Fluctuation ◽  
Surrounding Gate ◽  
Random Dopant

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

2020 ◽  
Vol 13 ◽  
Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu
Keyword(s):  
Monte Carlo ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Cmos Inverter ◽  
Back Gate ◽  
Random Dopant Fluctuation ◽  
Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

scholarly journals New Strategy for Analog Circuit Performance Evaluation under Disturbance and Fault Value

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Aihua Zhang ◽  
Yongchao Wang ◽  
Chen Chen ◽  
Hamid Reza Karimi
Keyword(s):  
Performance Evaluation ◽  
Support Vector Regression ◽  
Analog Circuit ◽  
Support Vector ◽  
Training Set ◽  
Circuit Performance ◽  
New Strategy ◽  
Indirect Evaluation ◽  
Novel Strategy ◽  
Fuzzy Learning

Focus on this issue of disturbance and fault value is inevitable in data collection about analog circuit. A novel strategy is developed for analog circuit online performance evaluation based on fuzzy learning and double weighted support vector machine (DWMK-FSVM). First, the double weighted support vector regression machine is employed to be the indirect evaluation means, relied on the college analog electronic technology experiment to evaluate analog circuit. Second, the superiority of fuzzy learning also is addressed to realize active suppression to the fault values and disturbance parameters. Moreover, the multikernel RBF is employed by support vector regression machine to realize more flexibility online such as the bandwidths tuning. Numerical results, supported by the college analog circuit experiments, adopted OTL performance eight indexes, which were obtained via precision instrument evaluation in two years to construct training set and are then to be evaluated online based on DWMK-FSVM. Simulation results presented not only highlight precision of the evaluation strategy derived here but also illustrate its great robustness.

Performance Improvements of Random Dopant Fluctuation-Induced Variability in Negative Capacitance MOSFETS

2019 ◽  
Vol 19 (01) ◽  
pp. 2050002
Author(s):  
W. F. Lü ◽  
L. Dai ◽  
Z. F. Zhao ◽  
M. Lin
Keyword(s):  
Performance Improvement ◽  
Decisive Role ◽  
Feedback Mechanism ◽  
Negative Capacitance ◽  
Performance Parameters ◽  
Performance Improvements ◽  
Random Dopant Fluctuation ◽  
Statistical Variations ◽  
The Impact ◽  
Random Dopant

In this paper, we investigate the impact of random dopant fluctuation (RDF) on the statistical variations in negative capacitance MOSFETs (NCFETs) through a device simulation coupled with the Landau–Khalatnikov (LK) equation. Compact models for feedback mechanisms that are based on the internal gate voltage amplification in NCFETs are proposed. The results show that internal voltage amplification plays a decisive role in performance improvement of device variability. Further, our simulation study demonstrates that owing to the feedback mechanism, the dispersions of the performance parameters in NCFETs exhibit different statistical distribution characteristics compared to their MOSFET counterparts. Our study may provide further insight regarding device and/or circuit designs utilizing NCFETs.

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