Magnetic Random Access Memory (MRAM)

2007 ◽  
Vol 7 (1) ◽  
pp. 117-137
Author(s):  
Yuankai Zheng ◽  
Yihong Wu ◽  
Kebin Li ◽  
Jinjun Qiu ◽  
Guchang Han ◽  
...  
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Random Access ◽  
High Density ◽  
Direct Writing ◽  
Cell Array ◽  
Cross Point ◽  
Reading And Writing ◽  
Cell Efficiency ◽  
Array Structures

The high density and high speed nonvolatile MTJ MRAMs are reviewed from perspective of the reading and writing operation. The reading operation of the MRAM with different sensing schemes and cell array structures is discussed, in particular the reference resistance generating schemes which are introduced to maximize the cell efficiency and reading reliability. The high density, low cost cross-point cell layout structures are analyzed systematically. The writing operation modes ranging from the half-select, toggle mode, guided SAF direct writing, thermally assisted writing, to the spin transfer switching are investigated both theoretically and experimentally. The thermal factor always plays an important role in determine not only the thermal stability but also the reading and writing reliability.

Prospect of Emerging Nonvolatile Memories

2004 ◽  
Vol 830 ◽  
Author(s):  
Hongsik Jeong ◽  
Kinam Kim
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Random Access ◽  
Random Access Memory ◽  
High Density ◽  
Access Memory ◽  
Flash Memories ◽  
Nonvolatile Memories ◽  
Critical Technology ◽  
The Future

ABSTRACTConventional nonvolatile memories such as Flash and EEPROM memory have successfully evolved toward high density and low cost. Especially, the market and density of flash memories has grown rapidly which leads semiconductor technology. However, there have been concerns about whether this successful progress can be maintained in the future nano era and can satisfy the requirement of diversified future IT market. Flash memories have the advantage of high density with small cell size and by contraries the disadvantage of slow writing speed and limited endurance. This slow writing speed and limited endurance is not aligned with the trend of high speed and reliability for future semiconductor memories.The future for these conventional nonvolatile memories forces many research groups and companies to develop alternative memories with ideal memory characteristics such as non-volatility, high density, high speed, and low power, which none of the conventional memories can satisfy at the same time.In this article, I will evaluate the characteristics of future nonvolatile memories such as ferroelectric random access memory (FRAM), magnetoresistive random access memory (MRAM) and phase change random access memory (PRAM). These memories have been recently evaluated because of the possibility that they can overcome the challenges that conventional memories are facing. Finally we will review critical technology barriers in developing future memory and predict the promising technology to overcome the barriers in conventional and emerging new memories, which will be technology guidelines for future memory development.

Simulation and Design of a Silicon Nanowire based Phase Change Memory Cell

2012 ◽  
Vol 1431 ◽  
Author(s):  
Ramin Banan Sadeghian ◽  
Yusuf Leblebici ◽  
Ali Shakouri
Keyword(s):  
Phase Change ◽  
High Speed ◽  
Low Cost ◽  
Silicon Nanowire ◽  
Phase Change Memory ◽  
Random Access ◽  
Memory Cell ◽  
Oxide Thickness ◽  
Nanowire Diameter ◽  
Change Memory

ABSTRACTIn this work we present preliminary calculations and simulations to demonstrate feasibility of programming a nanoscale Phase Change Random Access Memory (PCRAM) cell by means of a silicon nanowire ballistic transistor (SNWBT). Memory cells based on ballistic transistors bear the advantage of having a small size and high-speed operation with low power requirements. A one-dimensional MOSFET model (FETToy) was used to estimate the output current of the nanowire as a function of its diameter. The gate oxide thickness was 1.5 nm, and the Fermi level at source was set to -0.32 eV. For the case of VDS = VGS = 1 V, when the nanowire diameter was increased from 1 to 60 nm, the output power density dropped from 109 to 106 W cm-2 , while the current increased from 20 to 90 μA. Finite element electro-thermal analysis were carried out on a segmented cylindrical phase-change memory cell made of Ge2Sb2Te5 (GST) chalcogenide, connected in series to the SNWBT. The diameter of the combined device, d, and the aspect ratio of the GST region were selected so as to achieve optimum heating of the GST. With the assumption that the bulk thermal conductivity of GST does not change significantly at the nanoscale, it was shown that for d = 24 nm, a ‘reset’ programming current of ID = 80 μA can heat the GST up to its melting point. The results presented herein can help in the design of low cost, high speed, and radiation tolerant nanoscale PCRAM devices.

Characteristics of a System in a Package with Silver Wires

2015 ◽  
Vol 661 ◽  
pp. 121-127 ◽  
Author(s):  
Yeong Lin Lai ◽  
Wen Jung Chiang
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Signal Integrity ◽  
Random Access ◽  
Data Rate ◽  
Performance Requirement ◽  
Eye Diagram ◽  
Fine Pitch ◽  
Aperture Width ◽  
System On A Chip

The system in a package (SiP) including of a system on a chip (SoC) and a double-data-rate-three synchronous dynamic random access memory (DDR3 SDRAM) were studied with respect to the high-speed characteristics. The SiP was the multi-chip-module thin-profile fine-pitch ball grid array (MCM TFBGA) package with four-layer substrate. The high-speed 1600-Mbps data rate DDR3 signals were used in the signal integrity (SI) analysis. The SiP with low-cost silver (Ag) wires displayed a 500.18-ps aperture width in the eye diagram, which was successfully achieved signal integrity (SI) performance requirement. This work demonstrated the SiP with the Ag wires was the great potential solution for the advanced high-speed product applications.

scholarly journals Highly Reliable Memory Operation of High Density Three-Terminal Thyristor Random Access Memory

2021 ◽  
Author(s):  
Hyangwoo Kim ◽  
Hyeonsu Cho ◽  
Hyeon-Tak Kwak ◽  
Myunghae Seo ◽  
Seungho Lee ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
High Density ◽  
Data Retention ◽  
Access Memory ◽  
Cathode Voltage ◽  
Cross Point ◽  
Memory Array ◽  
Retention Characteristics ◽  
Power Operation

Abstract Three-terminal (3-T) thyristor random-access memory is explored for a next generation high-density nanoscale vertical cross-point array. The effects of standby voltages on the device are thoroughly investigated in terms of gate-cathode voltage (VGC,ST) and anode- cathode voltage (VAC,ST) in the standby state for superior data retention characteristics and low-power operation. The device with the optimized VGC,ST of -0.4 V and VAC,ST of 0.6 V shows the continuous data retention capability without refresh operation with a low standby current of 1.14 pA. In addition, a memory array operation scheme of 3-T TRAM is proposed to address array disturbance issues. The presented array operation scheme can efficiently minimize program, erase and read disturbances on unselected cells by adjusting gate-cathode voltage. The standby voltage turns out to be beneficial to improve retention characteristics: over 10 s. With the proposed memory array operation, 3-T TRAM can provide excellent data retention characteristics and high-density memory configurations comparable with or surpass conventional dynamic random-access memory (DRAM) technology.

scholarly journals Challenges and Applications of Emerging Nonvolatile Memory Devices

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 1029 ◽  
Author(s):  
Writam Banerjee
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Random Access ◽  
Random Access Memory ◽  
Spin Transfer Torque ◽  
High Density ◽  
Memory Storage ◽  
Access Memory ◽  
Ultra Low Power

Emerging nonvolatile memory (eNVM) devices are pushing the limits of emerging applications beyond the scope of silicon-based complementary metal oxide semiconductors (CMOS). Among several alternatives, phase change memory, spin-transfer torque random access memory, and resistive random-access memory (RRAM) are major emerging technologies. This review explains all varieties of prototype and eNVM devices, their challenges, and their applications. A performance comparison shows that it is difficult to achieve a “universal memory” which can fulfill all requirements. Compared to other emerging alternative devices, RRAM technology is showing promise with its highly scalable, cost-effective, simple two-terminal structure, low-voltage and ultra-low-power operation capabilities, high-speed switching with high-endurance, long retention, and the possibility of three-dimensional integration for high-density applications. More precisely, this review explains the journey and device engineering of RRAM with various architectures. The challenges in different prototype and eNVM devices is disused with the conventional and novel application areas. Compare to other technologies, RRAM is the most promising approach which can be applicable as high-density memory, storage class memory, neuromorphic computing, and also in hardware security. In the post-CMOS era, a more efficient, intelligent, and secure computing system is possible to design with the help of eNVM devices.

Embedded Si Fan Out: A Low Cost Wafer Level Packaging Technology Without Molding and De-bonding Processes

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-15
Author(s):  
Hong Xie ◽  
Daquan Yu ◽  
Zhenrui Huang ◽  
Zhiyi Xiao ◽  
Li Yang ◽  
...  
Keyword(s):  
Form Factor ◽  
High Speed ◽  
Low Cost ◽  
High Density ◽  
Wafer Level ◽  
Small Form ◽  
Wafer Level Packaging ◽  
Temporary Bonding ◽  
Small Form Factor ◽  
Si Wafer

The growing and diversifying system requirements have continued to drive the development of a variety of new package technologies and configurations: small form factor, low weight, low profile, high pin count and high speed and low cost. Embedded chip in EMC, also called fan-out wafer-level packaging (FOWLP), has been used in various products such as baseband, RF (radio frequency) transceiver, and PMICs (power management ICs). Currently, INFO technology developed by TSMC®, NANIUM® were in mass production for 3D integration for processor and memory, which inspires other packaging foundries to develop their own embedded FOWLP for the forecasted explosive growth of this market in the next few years. There are a number of challenges for FOWLP. For process point of view, temporary bonding and de-bonding are required. EMC wafers are difficult to handle due to its large warpage driven by the big CTE difference between the Si and molding material. In addition, the manufacturing of fine pitch RDL on EMC surface is also difficult. In this paper, the concept of wafer level embedded Si Fan-Out (eSiFO) technology was introduced and the development progress was reported. For eSiFO, cavities with certain depth were formed by Si dry etch. Then device dies were thinned to designed thickness. The dice were then placed into the cavities and bonded by the attached film on the bottom of the dice. A reconstructed wafer was formed. The micro gap between the chip and sidewall of the cavity as well as the surface of the reconstructed wafer were filled by dry film using vacuum process. Next, the pads were opened, followed RDL fabrication, repassivation, BGA, wafer thinning and dicing. Finally, an eSiFO package was fabricated. There are a number of advantages for eSiFO technology. There is nearly no warpage since the Si was used as reconstruct substrate. The process is relatively simple since no molding, temporary bonding and de-bonding are required. RDL manufacturing is easier on Si wafer vs with molding compounds and can achieve high density routing. Furthermore, it can provide small form factor since the thinning of wafer is the last step. To prove the concept of eSiFO, a 3.3 x 3.3mm package with 50 BGA bumps at 400μm pitch was fabricated. The device wafer was thinned to 100μm. The die size is 1.96 × 2.36mm with pad pitch at about 90μm. The depth of the cavities on 8 in. wafer formed by Bosch process on bare Si wafer was 107μm with 8μm variation. The length and width of Si cavities is 20μm larger than die size. In the package, there is one layer Cu RDL with thickness of 3μm, minimum line width of 13.72μm. The BGA ball diameter is 280μm. All the processes were evaluated and the results showed such packages can be produced. Reliability tests including THS, T/C, HTS and HAST were carried out and no failure issue was observed. Mechanical simulation was used to analyze the stress distribution during TC test and the results showed the maximum stress was located at the RDL near the UBM. In summary, a low cost wafer level fan out technology using reconstructed Si wafer was developed. The process is simple without molding, temporary bonding and de-bonding. The reliability tests of test vehicles proved that such package is reliable. The newly developed eSiFO technology can be widely used for chips requiring fan-Out, small form factor and high density interconnects.

scholarly journals Simple Absorbance-Based Assays for Ultra-High Throughput Screening

2001 ◽  
Vol 6 (1) ◽  
pp. 3-9 ◽  
Author(s):  
Patrick Lavery ◽  
Murray J.B. Brown ◽  
Andrew J. Pope
Keyword(s):  
High Throughput ◽  
High Throughput Screening ◽  
High Speed ◽  
Low Cost ◽  
High Density ◽  
Pharmaceutical Companies ◽  
Fluorescence Techniques ◽  
Enzyme Systems ◽  
Assay Performance ◽  
Standard Assay

In order to accommodate the predicted increase in screening required of successful pharmaceutical companies, miniaturized, high-speed HTS formats are necessary. Much emphasis has been placed on sensitive fluorescence techniques, but some systems, particularly enzymes interconverting small substrates, are likely to be refractory to such approaches. We show here that simple absorbance-based assays can be miniaturized to 10-,.d volumes in 1536- well microplates compatible with the requirements for ultra-high throughput screening. We demonstrate that, with low-cost hardware, assay performance is wholly predictable from the 2-fold decrease in pathlength for fully filled 1536-well plates compared to 96- and 384-well microplates. A number of enzyme systems are shown to work in this high-density format, and the inhibition parameters determined are comparable with those in standard assay formats. We also demonstrate the utility of kinetics measurements in miniaturized format with improvements in assay quality and the ability to extract detailed mechanistic information about inhibitors.

scholarly journals Modeling-Based Design of Memristive Devices for Brain-Inspired Computing

2021 ◽  
Vol 3 ◽  
Author(s):  
Yudi Zhao ◽  
Ruiqi Chen ◽  
Peng Huang ◽  
Jinfeng Kang
Keyword(s):  
Resistive Switching ◽  
High Speed ◽  
Data Transfer ◽  
Low Cost ◽  
Random Access ◽  
Processing Unit ◽  
Computing Systems ◽  
Stochastic Computing ◽  
Non Volatile Memory ◽  
Physical Effects

Resistive switching random access memory (RRAM) has emerged for non-volatile memory application with the features of simple structure, low cost, high density, high speed, low power, and CMOS compatibility. In recent years, RRAM technology has made significant progress in brain-inspired computing paradigms by exploiting its unique physical characteristics, which attempts to eliminate the energy-intensive and time-consuming data transfer between the processing unit and the memory unit. The design of RRAM-based computing paradigms, however, requires a detailed description of the dominant physical effects correlated with the resistive switching processes to realize the interaction and optimization between devices and algorithms or architectures. This work provides an overview of the current progress on device-level resistive switching behaviors with detailed insights into the physical effects in the resistive switching layer and the multifunctional assistant layer. Then the circuit-level physics-based compact models will be reviewed in terms of typical binary RRAM and the emerging analog synaptic RRAM, which act as an interface between the device and circuit design. After that, the interaction between device and system performances will finally be addressed by reviewing the specific applications of brain-inspired computing systems including neuromorphic computing, in-memory logic, and stochastic computing.

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