Life and Times of the Samson Box

2013 ◽  
Vol 37 (3) ◽  
pp. 26-48 ◽  
Author(s):  
D. Gareth Loy

Peter Samson designed and built a real-time signal-processing computer for music applications in the 1970s. The Systems Concepts Digital Synthesizer (“Samson Box” for short) was installed at the Center for Computer Research in Music and Acoustics (CCRMA) at Stanford University in 1977, where it served for over a decade as the principal music generation system. It was an important landmark in the transition from general-purpose computers to real-time systems for music and audio, and helped set the stage for the sea change in the music industry from analog to digital technologies that began in the 1980s and continues at a rapid pace today. This article focuses on the historical context of the Samson Box, its development, its impact on the culture of CCRMA and the Stanford Artificial Intelligence Laboratory, its use for music research and composition at Stanford, and its role in the transformation of the music and audio industries from analog to digital practices. A list of compositions realized on the Samson Box is included, which shows that from 1978 to its decommissioning in 1992 it was used to create over 100 finished works, many of which were widely performed and were awarded prizes. A companion article provides a detailed architectural review and an interview with Pete Samson.

2021 ◽  
Vol 31 ◽  
Author(s):  
BHARGAV SHIVKUMAR ◽  
JEFFREY MURPHY ◽  
LUKASZ ZIAREK

Abstract There is a growing interest in leveraging functional programming languages in real-time and embedded contexts. Functional languages are appealing as many are strictly typed, amenable to formal methods, have limited mutation, and have simple but powerful concurrency control mechanisms. Although there have been many recent proposals for specialized domain-specific languages for embedded and real-time systems, there has been relatively little progress on adapting more general purpose functional languages for programming embedded and real-time systems. In this paper, we present our current work on leveraging Standard ML (SML) in the embedded and real-time domains. Specifically, we detail our experiences in modifying MLton, a whole-program optimizing compiler for SML, for use in such contexts. We focus primarily on the language runtime, reworking the threading subsystem, object model, and garbage collector. We provide preliminary results over a radar-based aircraft collision detector ported to SML.


2013 ◽  
Vol 59 (10) ◽  
pp. 1405-1413 ◽  
Author(s):  
Ruhui Ma ◽  
Wei Ye ◽  
Alei Liang ◽  
Haibing Guan ◽  
Jian Li

2016 ◽  
Vol 10 (1) ◽  
pp. 13-22
Author(s):  
Ionel Zagan ◽  
Vasile Gheorghita Gaitan

Abstract The predictable CPU architectures that run hard real-time tasks must be executed with isolation in order to provide a timing-analyzable execution for real-time systems. The major problems for real-time operating systems are determined by an excessive jitter, introduced mainly through task switching. This can alter deadline requirements, and, consequently, the predictability of hard real-time tasks. New requirements also arise for a real-time operating system used in mixed-criticality systems, when the executions of hard real-time applications require timing predictability. The present article discusses several solutions to improve the performance of CPU architectures and eventually overcome the Operating Systems overhead inconveniences. This paper focuses on the innovative CPU implementation named nMPRA-MT, designed for small real-time applications. This implementation uses the replication and remapping techniques for the program counter, general purpose registers and pipeline registers, enabling multiple threads to share a single pipeline assembly line. In order to increase predictability, the proposed architecture partially removes the hazard situation at the expense of larger execution latency per one instruction.


2013 ◽  
Vol 738 ◽  
pp. 243-246
Author(s):  
Wang Da Chen ◽  
Yong Mao Cheng ◽  
Jian Cao ◽  
Hua Qin Liu

To meet the demand of communication automation for outfield equipment test module, special embedded system was proposed by combing host computer control board and signal acquisition board, taking advantage of high data transmission efficiency on PC104 bus. Multichannel switch, signal recuperation circuit and Analog to Digital Converter (ADC) were controlled by FPGA logic on signal acquisition board. Signal data acquired were transmitted to host computer control board to display for user in real time. Application shows that the system was easy to operate. It performs well on real time ability and stability.


Author(s):  
Jesus D. Terrazas Gonzalez ◽  
Mohamed Nasri ◽  
Tong Duan ◽  
Witold Kinsner

Teaching undergraduate students about interfacing of microprocessors and microcontrollers in real-time systems is challenging because the circuits have moved from medium to increasingly higher frequencies (multimega- and giga hertz), while wired interfacing has been augmented with wireless interfacing. The trend to design reliable and small-footprint complex digital subsystems also calls for field programmable gate arras (FPGAs). This paper describes an attempt to accommodate the changes through a development of a new FPGA-based lab in an undergraduate course called Microprocessor Interfacing (μI) that has been offered at the University of Manitoba for many years now [1-4]. The course presents real-time wired and wireless interfacing of microcontrollers, microprocessors, and microcomputers to the external world, including interfacing of input/output (I/O) devices with minimum hardware and software, as well as data acquisition with and without microprocessors, data communications, transmission and logging with embedded computers. The following topics are covered: (i) introduction on computing, architectures, processors, and technologies, (ii) architecture and organization of small computer buses, and synchronization of data transfers on local buses (iii) digital input and output (I/O), (iv) digital-to-analog (D/A) and analog-to-digital (A/D) signal conversions and converters, (v) and interfacing aspects in data communications, including encoding, modulation, error detection and forward error protection. The course also includes (a) demonstrations of bus architectures, modules, systems, and new devices, as well as (b) updates on new concepts, technologies, protocols, and software. The laboratories are innovative in terms of three levels of complexity: the Tier1 level includes five 3-hour standard labs designed for all students, the Tier2 is designed for more experienced students, and the Tier3 level lab is designed as a project for groups of students with demonstrated prior design and implementation experience [3]. This paper describes a new laboratory in this course designed to show how to achieve asynchronous data communications using both VLSI components and field programmable gate arrays (FPGA). The first embodiment is designed to illustrate the principles of operation, while the second is to demonstrate how complex functional subsystems can be implemented in FPGA reconfigurable hardware. The laboratory has been used in the course, and produced encouraging results.


IEE Review ◽  
1992 ◽  
Vol 38 (3) ◽  
pp. 112
Author(s):  
Stuart Bennett

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