scholarly journals Design of a CMOS Lineal Hall Sensor Front-End Working in Current Mode with Programmable Gain Stage for Power Specific Chip

2021 ◽  
Vol 2021 ◽  
pp. 1-5
Author(s):  
Peng Li ◽  
Wei Xi ◽  
Xianggen Yin ◽  
Hao Yao ◽  
Huafeng Chen
Keyword(s):  
Internet Of Things ◽  
Circuit Simulation ◽  
Current Mode ◽  
Cmos Technology ◽  
Hall Sensor ◽  
Total Power ◽  
Offset Voltage ◽  
Front End ◽  
Programmable Gain ◽  
Gain Stage

With the continuous intelligentization of power systems, the demand for the integration of digital chips and sensor chips such as the Internet of Things is also increasing. A CMOS lineal magnetic Hall sensor front-end working in current mode with programmable gain stage is designed and implemented with SMIC 55 nm standard CMOS technology. By using a spinning-current technique, chopper technique, and digital calibration technique to eliminate the offset voltage and nonlinearity, this magnetic Hall sensor can be easily integrated into digital systems like SoCs. This work has already finished the circuit simulation and layout design, and all simulation indicators basically reach the expected value. The maximum gain of proposed sensor systems can be up to 33.9 dB. The total power is less than 4 mW. And the total area is less than 0.113 μm2. The magnetic Hall sensor can be easily integrated into chips such as the power Internet of Things to form a single-chip-level SoC design, which is mainly used in applications such as circuit breakers and electric energy measurement.

scholarly journals 60 GHz Front-End Components for Broadband Wireless Communication in 130 nm CMOS Technology

2016 ◽  
Vol 21 (1) ◽  
pp. 67-77
Author(s):  
Vasilis Kolios ◽  
Konstantinos Giannakidis ◽  
Grigorios Kalivas
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Total Power ◽  
Spectral Space ◽  
60 Ghz ◽  
Front End ◽  
Total Power Consumption ◽  
5 Ghz

Abstract The over 5 GHz available spectral space allocated worldwide around the 60 GHz band, is very promising for very high data rate wireless short-range communications. In this article we present two key components for the 60 GHz front-end of a transceiver, in 130 nm RF CMOS technology: a single-balanced mixer with high Conversion Gain (CG), reduced Noise Figure (NF) and low power consumption, and an LC cross-coupled Voltage Controlled Oscillator (VCO) with very good linearity, with respect to Vctrl, and very low Phase Noise (PN). In both circuits, custom designed inductors and a balun structure for the mixer are employed, in order to enhance their performance. The VCO’s inductor achieves an inductance of 198 pH and a quality factor (Q) of 30, at 30 GHz. The balun shows less than 1o Phase Imbalance (PI) and less than 0.2 dB Amplitude Imbalance (AI), from 57 to 66 GHz. The mixer shows a CG greater than 15 dB and a NF lower than 12 dB. In addition, the VCO achieves a Phase Noise lower than -106 dBc/Hz at 1 MHz offset, and shows great linearity for the entire band. Both circuits are biased with a 1.2 V supply voltage and the total power consumption is about 10.6 mW for the mixer and 10.92 mW for the VCO.

scholarly journals 1.5-V CMOS Current Multiplier/Divider

2018 ◽  
Vol 8 (3) ◽  
pp. 1478 ◽  
Author(s):  
Jetsdaporn Satansup ◽  
Worapong Tangsrirat
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Signal Frequency ◽  
Total Power ◽  
Total Power Consumption ◽  
Linearity Error ◽  
Low Supply Voltage ◽  
Circuit Technique

A circuit technique for designing a compact low-voltage current-mode multiplier/divider circuit in CMOS technology is presented.  It is based on the use of a compact current quadratic cell able to operate at low supply voltage.  The proposed circuit is designed and simulated for implementing in TSMC 0.25-m CMOS technology with a single supply voltage of 1.5 V.  Simulation results using PSPICE, accurately agreement with theoretical ones, have been provided, and also demonstrate a maximum linearity error of 1.5%, a THD less than 2% at 100 MHz, a total power consumption of 508 W, and -3dB small-signal frequency of about 245 MHz.

scholarly journals A CMOS Current-Mode Magnetic Hall Sensor With Integrated Front-End

2015 ◽  
Vol 62 (5) ◽  
pp. 1270-1278 ◽  
Author(s):  
Hadi Heidari ◽  
Edoardo Bonizzoni ◽  
Umberto Gatti ◽  
Franco Maloberti
Keyword(s):  
Current Mode ◽  
Hall Sensor ◽  
Front End

A 10Gb/s Low-Power Front-End Amplifier for Optical Receiver in 0.18μm CMOS Technology

2012 ◽  
Vol 588-589 ◽  
pp. 872-875 ◽  
Author(s):  
Zhu Lei ◽  
Ying Mei Chen ◽  
Ling Tian ◽  
Li Zhang
Keyword(s):  
Cmos Technology ◽  
Optical Receiver ◽  
Transimpedance Amplifier ◽  
Chip Area ◽  
Limiting Amplifier ◽  
Front End ◽  
Active Feedback ◽  
Common Gate ◽  
The Common ◽  
Gain Stage

A Front-End Amplifier for the STM-64(10Gb/s) optical receiver in SDH system has been proposed in TSMC 0.18 μm CMOS technology. The common-gate feedforward configuration with an active inductor is employed in the input stage of transimpedance amplifier to increase the bandwidth. A 3-order interleaving active feedback configuration is employed to expand the bandwidth in the gain stage of transimpedance amplifier and limiting amplifier. Simulation results show that the output swing is 190mV (Vpp) when the input current varies from 20μA to 400μA. The power consumption is only 98.2mW with 1.8V power supply and the chip area is 496μm×480μm.

A 75dB Programmable Gain Amplifier for Dual Mode Wireless Receivers

2012 ◽  
Vol 229-231 ◽  
pp. 1609-1613
Author(s):  
Xiang Ning Fan ◽  
Kuan Bao ◽  
Da Chen ◽  
Liang Yi Ma
Keyword(s):  
Supply Voltage ◽  
Cmos Technology ◽  
Dual Mode ◽  
Peak Voltage ◽  
Dc Offset ◽  
Variable Gain ◽  
Gain Error ◽  
Programmable Gain Amplifier ◽  
Programmable Gain ◽  
Gain Stage

In this paper, a programmable gain amplifier (PGA) is designed and implemented for GPS/Galileo and WCDMA dual mode receiver using TSMC 0.18μm CMOS technology. The 0-75dB variable gain range is obtained by cascading a 0-15dB variable gain stage and four 15dB fixed gain stages. An open-loop structured fully-differential amplifier with source feedback resistor is adopted in basic gain stage. Variation of gain is achieved by switch-controlled output resistor network. Gm-boost structure is used in main amplifier. A DC-offset canceller circuit using DC negative feedback technique is proposed to eliminate the DC-offset of the PGA. Post-simulation shows that the PGA has 0-75dB variable gain range, 1dB gain resolution and less than 0.3dB gain error; the minimum DC attenuation is about 15dB over the whole gain range; -3dB bandwidth at the maximum gain configuration is about 15MHz; differential output peak to peak voltage is greater than 1V; and the entire circuit consumes about 3.6mA current under 1.8V supply voltage.

CURRENT FEEDBACK OP-AMP UTILIZES NEW CURRENT CELL TO ENHANCE THE CMRR

2012 ◽  
Vol 21 (05) ◽  
pp. 1250038 ◽  
Author(s):  
AMR ABDALLAH TAMMAM ◽  
MOHAMED BEN-ESMAEL ◽  
MOHAMMED R. ABAZAB
Keyword(s):  
Operational Amplifier ◽  
High Speed ◽  
Circuit Simulation ◽  
Current Mode ◽  
Current Feedback ◽  
Output Resistance ◽  
Common Mode ◽  
Offset Voltage ◽  
Current Cell ◽  
Current Feedback Operational Amplifier

Despite excellent high frequency and high speed performance, current-feedback operational amplifiers (CFOAs) generally exhibit poor common-mode rejection (CMRR) properties, which limit their utility [Analogue IC design: The current–mode approach, IEE Circuits and Systems Series, Peter peregrinus, 1990]. A novel current feedback operational amplifier (CFOA) with improved performance is presented. The proposed CFOA has a new current-cell [Novel current-feedback operational amplifier Design Based on a floating circuit technique, IEE Colloquium on Analogue Signal Processing, 1998], to bias the entire circuit, which achieves an incremental output resistance twice that of the well-known "Wilson" circuit. Simulation results of this new CFOA architecture indicate that the amplifier exhibits performance characteristics superior to those obtained with an established input architecture: in particular, the CMRR (common-mode rejection ratio) is 91 dB, and the d.c. offset voltage less than 26 μV.

A biasing based current mode analog front-end for biomedical applications

2021 ◽  
Author(s):  
Raja Krishnamoorthy ◽  
E. Kavitha ◽  
V. Beslin Geo ◽  
K.S.R. Radhika ◽  
C. Bharatiraja
Keyword(s):  
Biomedical Applications ◽  
Current Mode ◽  
Front End ◽  
Analog Front End

CMOS-MEMS Based Current Mirror MOSFET Embedded Pressure Sensor for Healthcare and Biomedical Applications

2013 ◽  
Vol 647 ◽  
pp. 315-320 ◽  
Author(s):  
Pradeep Kumar Rathore ◽  
Brishbhan Singh Panwar
Keyword(s):  
Pressure Sensor ◽  
Biomedical Applications ◽  
Circuit Simulation ◽  
Applied Pressure ◽  
Pressure Sensors ◽  
Cmos Technology ◽  
Current Mirror ◽  
Sensing Element ◽  
Pressure Sensing ◽  
Cmos Mems

This paper reports on the design and optimization of current mirror MOSFET embedded pressure sensor. A current mirror circuit with an output current of 1 mA integrated with a pressure sensing n-channel MOSFET has been designed using standard 5 µm CMOS technology. The channel region of the pressure sensing MOSFET forms the flexible diaphragm as well as the strain sensing element. The piezoresistive effect in MOSFET has been exploited for the calculation of strain induced carrier mobility variation. The output transistor of the current mirror forms the active pressure sensing MOSFET which produces a change in its drain current as a result of altered channel mobility under externally applied pressure. COMSOL Multiphysics is utilized for the simulation of pressure sensing structure and Tspice is employed to evaluate the characteristics of the current mirror pressure sensing circuit. Simulation results show that the pressure sensor has a sensitivity of 10.01 mV/MPa. The sensing structure has been optimized through simulation for enhancing the sensor sensitivity to 276.65 mV/MPa. These CMOS-MEMS based pressure sensors integrated with signal processing circuitry on the same chip can be used for healthcare and biomedical applications.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

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