scholarly journals Master-Slave Topologies with Phase-Locked Loops

2020 ◽  
Vol 2020 ◽  
pp. 1-12
Author(s):  
José Roberto C. Piqueira
Keyword(s):  
Integrated Circuits ◽  
Communication Networks ◽  
Smart Grids ◽  
Essential Element ◽  
Recovery Process ◽  
Distribution Networks ◽  
Phase Locked Loops ◽  
Signal Recovery ◽  
Clock Signal ◽  
Clock Distribution

Since phase-locked loops (PLLs) were conceived by Bellescize in 1932, their presence has become almost mandatory in any telecommunication device or network, being the essential element to recover frequency and phase information. As the technology developed, PLL appeared in several applications, such as, dense communication networks, smart grids, electronic instrumentation, computational clusters, and integrated circuits. In all of these practical cases, isolated or networked PLLs are responsible for recovering the correct time basis and synchronizing the processes. According to the application needs, different clock distribution strategies were developed, with the master-slave being the simplest and most used choice. Considering that the master clock is obtained from a stable periodic oscillator, two topologies are studied: one-way, not considering clock feedback; and two-way master-slave, with the slave nodes providing clock feedback to the master. Here, these two cases are studied by using simulation strategies, presenting results about the clock signal recovery process in the presence of disturbances, indicating that master-slave clock distribution networks can be useful for networks with few nodes and a stable master oscillator with the one-way topology presenting better results than the two-way arrangement.

scholarly journals Evaluation of the Use of Class B LoRaWAN for the Coordination of Distributed Interface Protection Systems in Smart Grids

2020 ◽  
Vol 9 (1) ◽  
pp. 13 ◽  
Author(s):  
Marco Pasetti ◽  
Emiliano Sisinni ◽  
Paolo Ferrari ◽  
Stefano Rinaldi ◽  
Alessandro Depari ◽  
...  
Keyword(s):  
Response Time ◽  
Communication Networks ◽  
Smart Grids ◽  
Distribution Networks ◽  
Maximum Response ◽  
Area Network ◽  
Wide Area Network ◽  
Protection Systems ◽  
Class B ◽  
Maximum Response Time

The adoption of the distributed generation paradigm is introducing several changes in the design and operation of modern distribution networks. Modern grid codes are becoming more and more complex, and the adoption of smart protection systems is becoming mandatory. However, the adoption of newer and smarter units is only half of the story. Proper communication networks must be provided as well, and the overall costs may become critical. In this work, the adoption of the Long-Range Wide Area Network (LoRaWAN) technology is suggested as a viable approach to implement the coordination of Interface Protection Systems. A proper communication architecture based on the LoRaWAN Class B technology was proposed and evaluated in order to assess its feasibility for the considered application. A scalability analysis was carried out, by computing the number of devices that can be handled by a single LoRaWAN Gateway (GW) and the maximum expected time of response between a triggering event and the arrival of the related coordination command. The results of the study showed that up to 312 devices can be managed by a single GW, by assuring a maximum response time of 22.95 s. A faster maximum response time of 6.2 s is also possible by reducing the number of managed devices to 12.

scholarly journals Fully Connected PLL Networks: How Filter Determines the Number of Nodes

2009 ◽  
Vol 2009 ◽  
pp. 1-13 ◽  
Author(s):  
Átila Madureira Bueno ◽  
André Alves Ferreira ◽  
José Roberto C. Piqueira
Keyword(s):  
Integrated Circuits ◽  
Distribution Systems ◽  
Second Order ◽  
Phase Locked Loops ◽  
Clock Distribution ◽  
Synchronous State ◽  
First Order ◽  
Automation Systems ◽  
Low Pass ◽  
Fully Connected

Synchronization plays an important role in telecommunication systems, integrated circuits, and automation systems. Formerly, the masterslave synchronization strategy was used in the great majority of cases due to its reliability and simplicity. Recently, with the wireless networks development, and with the increase of the operation frequency of integrated circuits, the decentralized clock distribution strategies are gaining importance. Consequently, fully connected clock distribution systems with nodes composed of phase-locked loops (PLLs) appear as a convenient engineering solution. In this work, the stability of the synchronous state of these networks is studied in two relevant situations: when the node filters are first-order lag-lead low-pass or when the node filters are second-order low-pass. For first- order filters, the synchronous state of the network shows to be stable for any number of nodes. For second-order filter, there is a superior limit for the number of nodes, depending on the PLL parameters.

Comparing LQG/LTR and the SDRE Techniques for Hybrid Fully-Connected PLL Network Control

2013 ◽  
Author(s):  
Átila Madureira Bueno ◽  
Angelo Marcelo Tusset ◽  
Diego Paolo Ferruzzo Correa ◽  
José Roberto Castilho Piqueira ◽  
José Manoel Balthazar
Keyword(s):  
Integrated Circuits ◽  
Network Control ◽  
Clock Signal ◽  
Clock Distribution ◽  
Signal Distribution ◽  
Performance Requirements ◽  
Distribution Process ◽  
And Performance ◽  
The Stability ◽  
Fully Connected

Synchronization plays an important role in telecommunication systems and integrated circuits. The Master-Slave is a commonly used strategy for clock signal distribution. However, due to the wireless networks development and the higher operation frequency of integrated circuits, the Mutually-Connected clock distribution strategies are becoming important, and the Fully-Connected strategy appears as a convenient engineering solution. The main drawback of the Fully-Connected architecture is the definition of control algorithms that assure the stability of the network sinchronization. In hybrid synchronization techniques groups of nodes synchronized by the Fully-Connected architecture are synchronized with network master clocks by using the Master-Slave tecnique. In this arrangement, if a route of clock signal distribution becomes inoperative, the group of Fully-Connected nodes retain for some time the original phase and frequency received from the network. The Fully-Connected architecture complexity imposes difficulties to satisfy both stability and performance requirements in the control system design. For that reason the multi-variable LQG/LTR and the SDRE control techniques are applied in order to fulfill both stability and performance requirements. The performance of both techniques are compared, and the results seems to confirm the improvement in the transient response and in the precision of the clock distribution process.

scholarly journals Models for Master-Slave Clock Distribution Networks with Third-Order Phase-Locked Loops

2007 ◽  
Vol 2007 ◽  
pp. 1-17 ◽  
Author(s):  
José Roberto Castilho Piqueira ◽  
Marcela de Carvalho Freschi
Keyword(s):  
Numerical Experiments ◽  
Phase Synchronization ◽  
Distribution Networks ◽  
Phase Locked Loops ◽  
Clock Distribution ◽  
Third Order ◽  
Clock Distribution Networks ◽  
Priority Scheme ◽  
Geographically Distributed ◽  
Lock In

The purpose of this work is to study the processing and transmission of clock signals in networks of geographically distributed nodes, in order to derive conditions for frequency and phase synchronization between the nodes. The focus is on the master-slave architecture, which presents a priority scheme of clock distribution. One-way master-slave (OWMS ) and two-way master-slave (TWMS) chains are studied, considering that the slave nodes are third-order phase-locked loops (PLLs). Third-order PLLs are chosen to improve the transient response but, if their parameters are not well adjusted, stability problems and chaotic behaviors appear, restricting the lock-in range of the network. Lock-in range for third-order PLLs with Sallen-Key filter is determined and it is verified whether this range is reduced when the PLLs are connected to a network. Numerical experiments show how chain size changes the lock-in ranges and the acquisition times.

scholarly journals Automated Synthesis of Skew-Based Clock Distribution Networks

VLSI Design ◽  
1998 ◽  
Vol 7 (1) ◽  
pp. 31-57 ◽  
Author(s):  
José Luis Neves ◽  
Eby G. Friedman
Keyword(s):  
Distribution Network ◽  
Distribution Networks ◽  
Clock Signal ◽  
Clock Distribution ◽  
Delay Model ◽  
Clock Skew ◽  
Clock Tree ◽  
Clock Distribution Networks ◽  
Clock Distribution Network ◽  
Interconnect Lines

In this paper a top-down methodology is presented for synthesizing clock distribution networks based on application-dependent localized clock skew. The methodology is divided into four phases: 1) determination of an optimal clock skew schedule for improving circuit performance and reliability; 2) design of the topology of the clock tree based on the circuit hierarchy and minimum clock path delays; 3) design of circuit structures to implement the delay values associated with the branches of the clock tree; and 4) design of the geometric layout of the clock distribution network. Algorithms to determine an optimal clock skew schedule, the optimal clock delay to each register, the network topology, and the buffer circuit dimensions are presented.The clock distribution network is implemented at the circuit level in CMOS technology and a design strategy based on this technology is presented to implement the individual branch delays. The minimum number of inverters required to implement the branch delays is determined, while preserving the polarity of the clock signal. The clock lines are transformed from distributed resistive-capacitive interconnect lines into purely capacitive interconnect lines by partitioning the RC interconnect lines with inverting repeaters. The inverters are specified by the geometric size of the transistors, the slope of the ramp shaped input/output waveform, and the output load capacitance. The branch delay model integrates an inverter delay model with an interconnect delay model. Maximum errors of less than 2.5% for the delay of the clock paths and 4% for the clock skew between any two registers belonging to the same global data path are obtained as compared with SPICE Level-3.

Network analysis models – the secret for success

2004 ◽  
Vol 4 (5-6) ◽  
pp. 383-388
Author(s):  
D.M. Rogers
Keyword(s):  
Mathematical Model ◽  
Field Data ◽  
Essential Element ◽  
Distribution Networks ◽  
Automatic Calibration ◽  
Supply And Distribution ◽  
The World ◽  
Optimum Approach ◽  
Analysis Models

Water is a fundamental necessity of life. Yet water supply and distribution networks the world over are old and lacking in adequate maintenance. Consequently they often leak as much water as they deliver and provide an unacceptable quality of service to the customer. In certain parts of the world, water is available only for a few hours of the day. The solution is to build a mathematical model to simulate the operation of the real network in all of its key elements and apply it to optimise its operation. To be of value, the results of the model must be compared with field data. This process is known as calibration and is an essential element in the construction of an accurate model. This paper outlines the optimum approach to building and calibrating a mathematical model and how it can be applied to automatic calibration systems.

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