scholarly journals Test Point Selection Method for Analog Circuit Fault Diagnosis Based on Similarity Coefficient

2018 ◽  
Vol 2018 ◽  
pp. 1-11 ◽  
Author(s):  
Qingfeng Ma ◽  
Yuzhu He ◽  
Fuqiang Zhou ◽  
Ping Song

The demand for testability analysis has increased with the integration densities and complexity of circuits. As an important part of testability analysis, the test point selection method needs to be researched in depth. A new similarity coefficient criterion is proposed to determine the fault isolation degree because output responses of a circuit with component tolerance are approximately subject to the normal distribution. Then, a new test point selection method is proposed based on the fault-pair similarity coefficient criterion information table. Simulation experiments are used to validate the accuracy of the proposed method in terms of the optimum test point set and fault isolation degree. The results show that the proposed method improves the performance of test point selection by comparing with the other reported methods.

2014 ◽  
Vol 2014 ◽  
pp. 1-16 ◽  
Author(s):  
Yuan Gao ◽  
Chenglin Yang ◽  
Shulin Tian ◽  
Fang Chen

By simplifying tolerance problem and treating faulty voltages on different test points as independent variables, integer-coded table technique is proposed to simplify the test point selection process. Usually, simplifying tolerance problem may induce a wrong solution while the independence assumption will result in over conservative result. To address these problems, the tolerance problem is thoroughly considered in this paper, and dependency relationship between different test points is considered at the same time. A heuristic graph search method is proposed to facilitate the test point selection process. First, the information theoretic concept of entropy is used to evaluate the optimality of test point. The entropy is calculated by using the ambiguous sets and faulty voltage distribution, determined by component tolerance. Second, the selected optimal test point is used to expand current graph node by using dependence relationship between the test point and graph node. Simulated results indicate that the proposed method more accurately finds the optimal set of test points than other methods; therefore, it is a good solution to minimize the size of the test point set. To simplify and clarify the proposed method, only catastrophic and some specific parametric faults are discussed in this paper.


2011 ◽  
Vol 18 (1) ◽  
pp. 115-128 ◽  
Author(s):  
Andrzej Pułka

Two Heuristic Algorithms for Test Point Selection in Analog Circuit Diagnoses The paper presents a heuristic approach to the problem of analog circuit diagnosis. Different optimization techniques in the field of test point selection are discussed. Two new algorithms: SALTO and COSMO have been introduced. Both searching procedures have been implemented in a form of the expert system in PROLOG language. The proposed methodologies have been exemplified on benchmark circuits. The obtained results have been compared to the others achieved by different approaches in the field and the benefits of the proposed methodology have been emphasized. The inference engine of the heuristic algorithms has been presented and the expert system knowledge-base construction discussed.


2010 ◽  
Vol 26 (5) ◽  
pp. 523-534 ◽  
Author(s):  
ChengLin Yang ◽  
ShuLin Tian ◽  
Bing Long ◽  
Fang Chen

2015 ◽  
Vol 2015 ◽  
pp. 1-9
Author(s):  
Hongzhi Hu ◽  
Shulin Tian ◽  
Qing Guo

This paper deals with the modeling of fault for analog circuits. A two-dimensional (2D) fault model is first proposed based on collaborative analysis of supply current and output voltage. This model is a family of circle loci on the complex plane, and it simplifies greatly the algorithms for test point selection and potential fault simulations, which are primary difficulties in fault diagnosis of analog circuits. Furthermore, in order to reduce the difficulty of fault location, an improved fault model in three-dimensional (3D) complex space is proposed, which achieves a far better fault detection ratio (FDR) against measurement error and parametric tolerance. To address the problem of fault masking in both 2D and 3D fault models, this paper proposes an effective design for testability (DFT) method. By adding redundant bypassing-components in the circuit under test (CUT), this method achieves excellent fault isolation ratio (FIR) in ambiguity group isolation. The efficacy of the proposed model and testing method is validated through experimental results provided in this paper.


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