scholarly journals Corrigendum to “An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization”

2018 ◽  
Vol 2018 ◽  
pp. 1-1
Author(s):  
O. Ahmed ◽  
S. Areibi ◽  
R. Collier ◽  
G. Grewal
2013 ◽  
Vol 2013 ◽  
pp. 1-23 ◽  
Author(s):  
O. Ahmed ◽  
S. Areibi ◽  
R. Collier ◽  
G. Grewal

Current software-based packet classification algorithms exhibit relatively poor performance, prompting many researchers to concentrate on novel frameworks and architectures that employ both hardware and software components. The Packet Classification with Incremental Update (PCIU) algorithm, Ahmed et al. (2010), is a novel and efficient packet classification algorithm with a unique incremental update capability that demonstrated excellent results and was shown to be scalable for many different tasks and clients. While a pure software implementation can generate powerful results on a server machine, an embedded solution may be more desirable for some applications and clients. Embedded, specialized hardware accelerator based solutions are typically much more efficient in speed, cost, and size than solutions that are implemented on general-purpose processor systems. This paper seeks to explore the design space of translating the PCIU algorithm into hardware by utilizing several optimization techniques, ranging from fine grain to coarse grain and parallel coarse grain approaches. The paper presents a detailed implementation of a hardware accelerator of the PCIU based on an Electronic System Level (ESL) approach. Results obtained indicate that the hardware accelerator achieves on average 27x speedup over a state-of-the-art Xeon processor.


2011 ◽  
Vol 2011 ◽  
pp. 1-21 ◽  
Author(s):  
O. Ahmed ◽  
S. Areibi ◽  
K. Chattha ◽  
B. Kelly

Packet classification plays a crucial role for a number of network services such as policy-based routing, firewalls, and traffic billing, to name a few. However, classification can be a bottleneck in the above-mentioned applications if not implemented properly and efficiently. In this paper, we propose PCIU, a novel classification algorithm, which improves upon previously published work. PCIU provides lower preprocessing time, lower memory consumption, ease of incremental rule update, and reasonable classification time compared to state-of-the-art algorithms. The proposed algorithm was evaluated and compared to RFC and HiCut using several benchmarks. Results obtained indicate that PCIU outperforms these algorithms in terms of speed, memory usage, incremental update capability, and preprocessing time. The algorithm, furthermore, was improved and made more accessible for a variety of applications through implementation in hardware. Two such implementations are detailed and discussed in this paper. The results indicate that a hardware/software codesign approach results in a slower, but easier to optimize and improve within time constraints, PCIU solution. A hardware accelerator based on an ESL approach using Handel-C, on the other hand, resulted in a 31x speed-up over a pure software implementation running on a state of the art Xeon processor.


Author(s):  
Alan Kennedy ◽  
Zhen Liu ◽  
Xiaojun Wang ◽  
Bin Liu

2014 ◽  
Vol 1 ◽  
pp. 29-32
Author(s):  
Kazushige Nakamura ◽  
Kei Sumiyoshi ◽  
Noriko Hiroi ◽  
Akira Funahashi
Keyword(s):  

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