scholarly journals Modeling and Modulation of NNPC Four-Level Inverter for Solar Photovoltaic Power Plant

2017 ◽  
Vol 2017 ◽  
pp. 1-8 ◽  
Author(s):  
Xiaoqiang Guo ◽  
Xuehui Wang ◽  
Ran He ◽  
Mehdi Narimani

Photovoltaic (PV) power plant is an attractive way of utilizing the solar energy. For high-power PV power plant, the multilevel inverter is of potential interest. In contrast to the neutral-point clamped (NPC) or flying capacitor (FC) multilevel inverter, the nested neutral point clamped (NNPC) four-level inverter has better features for solar photovoltaic power plant. In practical applications, the common mode voltage reduction of the NNPC four-level is one of the important issues. In order to solve the problem, a new modulation strategy is proposed to minimize the common mode voltage. Compared with the conventional solution, our proposal can reduce the common mode voltage to 1/18 of the DC bus voltage. Moreover, it has the capability to balance the capacitor voltages. Finally, we carried out time-domain simulations to test the performance of the NNPC four-level inverter.

2016 ◽  
Vol 2016 ◽  
pp. 1-8 ◽  
Author(s):  
Xiaoqiang Guo ◽  
Ran He ◽  
Mehdi Narimani

Solar photovoltaic (PV) power plant is an effective way to utilize the renewable energy sources. EMI is one of the major concerns in PV power plant. Typically, the multilevel inverters are used in high voltage PV power plant. However, the conventional multilevel inverters require more semiconductors, which complicate the circuit structure and control algorithm. In this paper, a novel five-level inverter is introduced for the high voltage PV power plant applications. The model of the inverter is analyzed. With the redundant switching states, a new modulation strategy is proposed to reduce the common-mode voltage and EMI. The proposed approach is able to eliminate the common-mode voltage; meanwhile it has the capability of balancing the capacitor voltages. The cosimulation tests with the Matlab/Simulink and S-function are carried out. The results verify the effectiveness of the proposed method.


Author(s):  
C. Bharatiraja ◽  
J.L. Munda ◽  
N. Sriramsai ◽  
T Sai Navaneesh

The purpose of this paper is to provide a comprehensive Investigations and its control on the common mode Voltage (CMV) of the three-phase three-level neutral-point diode-clamped (NPC) multilevel inverter (MLI). A widespread space-vector pulse width modulation (SVPWM) technique to mitigate the perpetual problem of the NPC-MLI, the CMV, proposed. The proposed scheme is an effectual blend of nearest three vector (NTV) and selected three vector (STV) techniques. This scheme is capable to reduce the CMV without compromise the inverter output voltage and Total harmonics distraction (THD). CMV reduction achieved less than +Vdc/6 using the proposed vector selection procedure. The theoretical Investigations, the MATLAB software based computer simulation and Field Programmable Gate Array (FPGA) supported hardware corroboration have shown the superiority of the proposed technique over the conventional SVPWM schemes.


Energies ◽  
2019 ◽  
Vol 12 (5) ◽  
pp. 779 ◽  
Author(s):  
Ming Wu ◽  
Zhenhao Song ◽  
Zhipeng Lv ◽  
Kai Zhou ◽  
Qi Cui

To suppress the direct current (DC) capacitor voltage fluctuations and the common-mode voltage (CMV) in a three-phase, five-level, neutral-point-clamped (NPC)/H-bridge inverter, this paper analyzes the influence of all voltage vectors on the neutral point potential of each phase under different pulse mappings in detail with an explanation of the CMV distribution. Then, based on the traditional space vector pulse width modulation (SVPWM) algorithm, a dual-pulse-mapping algorithm is proposed to suppress the DC capacitor fluctuations and the CMV simultaneously. In the algorithm, the reference voltage synthesis selects the voltage vector that has the smallest CMV value as the priority. In addition, the two kinds of pulse mappings that have opposite effects on the neutral point potential are switched to output. At the same time, regulating factors are introduced to adjust the working time of each voltage vector under the two pulse mappings; then, the capacitor voltages can be balanced. Both the simulation and experiment demonstrate the algorithm’s effectiveness.


Energy ◽  
2021 ◽  
Vol 219 ◽  
pp. 119610
Author(s):  
S. Sreenath ◽  
K. Sudhakar ◽  
Yusop AF

Sign in / Sign up

Export Citation Format

Share Document