scholarly journals XOR-FREE Implementation of Convolutional Encoder for Reconfigurable Hardware

2016 ◽  
Vol 2016 ◽  
pp. 1-8 ◽  
Author(s):  
Gaurav Purohit ◽  
Kota Solomon Raju ◽  
Vinod Kumar Chaubey
Keyword(s):  
Propagation Delay ◽  
Code Rate ◽  
Reconfigurable Hardware ◽  
Lookup Table ◽  
Hardware Cost ◽  
Matlab Simulink ◽  
Generator Polynomial ◽  
Dynamic Power ◽  
Constraint Length ◽  
Convolutional Encoder

This paper presents a novel XOR-FREE algorithm to implement the convolutional encoder using reconfigurable hardware. The approach completely removes the XOR processing of a chosen nonsystematic, feedforward generator polynomial of larger constraint length. The hardware (HW) implementation of new architecture uses Lookup Table (LUT) for storing the parity bits. The design implements architectural reconfigurability by modifying the generator polynomial of the same constraint length and code rate to reduce the design complexity. The proposed architecture reduces the dynamic power up to 30% and improves the hardware cost and propagation delay up to 20% and 32%, respectively. The performance of the proposed architecture is validated in MATLAB Simulink and tested on Zynq-7 series FPGA.

Practical Realization of Multiple-Input Exclusive-OR Circuits for Low-Power Applications

1997 ◽  
Vol 07 (01) ◽  
pp. 31-48
Author(s):  
Kun-Jin Lin ◽  
Cheng-Wen Wu
Keyword(s):  
Low Power ◽  
Power Saving ◽  
Propagation Delay ◽  
Hardware Cost ◽  
The Past ◽  
Product Term ◽  
Multiple Input ◽  
Logic Structures ◽  
Exclusive Or ◽  
Reduction In Area

CMOS Exclusive-OR (EXOR) gate implementation using conventional logic structures results in high hardware cost and long propagation delay, making it unattractive to logic designers. A number of more efficient two-input CMOS EXOR-gate structures with only six transistors have been proposed in the past. In many applications, such as parity generator, checker, and Exclusive-OR Sum-of-Product (ESOP) circuits, multiple-input EXOR circuits are required. Two kinds of multiple-input EXOR circuit structures are presented, which are smaller, faster, and more power-saving than those formed by simply connecting two-input EXOR gates in a conventional way. The proposed structures are shown to be suitable for ESOP circuits in which four transistors can be saved for each product term. The reduction in area and power makes them attractive for low-power required applications such as mobile computing and wireless communications.

DYNAMIC POWER DISSIPATION FORMULATION FOR APPLICATION IN DYNAMIC PROGRAMMING BUFFER INSERTION ALGORITHM

2016 ◽  
Vol 78 (11) ◽  
Author(s):  
Chessda Uttraphan ◽  
Nasir Shaikh-Husin ◽  
M. Khalil-Hani
Keyword(s):  
Dynamic Programming ◽  
Closed Form ◽  
Power Dissipation ◽  
Closed Form Solution ◽  
Propagation Delay ◽  
Form Solution ◽  
Buffer Insertion ◽  
Dynamic Power ◽  
Insertion Algorithm ◽  
Series Of Experiments

Buffer insertion is a very effective technique to reduce propagation delay in nano-metre VLSI interconnects. There are two techniques for buffer insertion which are: (1) closed-form solution and (2) dynamic programming. Buffer insertion algorithm using dynamic programming is more useful than the closed-form solution as it allows the use of multiple buffer types and it can be used in tree structured interconnects. As design dimension shrinks, more buffers are needed to improve timing performance. However, the buffer itself consumes power and it has been shown that power dissipation of buffers is significant. Although there are many buffer insertion algorithms that were able to optimize propagation delay with power constraint, most of them used the closed-form solution. Hence, in this paper, we present a formulation to compute dynamic power dissipation of buffers for application in dynamic programming buffer insertion algorithm. The proposed formulation allows dynamic power dissipation of buffers to be computed incrementally. The technique is validated by comparing the formulation with the standard closed-form dynamic power equation. The advantage of the proposed formulation is demonstrated through a series of experiments where it is applied in van Ginneken’s algorithm. The results show that the output of the proposed formulation is consistent with the standard closed-form formulation. Furthermore, it also suggests that the proposed formulation is able to compute dynamic power dissipation for buffer insertion algorithm with multiple buffer types.  

Impact of code rate and constraint length variation on qualitative performance of OIDMA system with random inter-leaver

Optik ◽  
2020 ◽  
Vol 202 ◽  
pp. 163584
Author(s):  
Ajay Kumar Maurya ◽  
Ravi Prakash ◽  
S.K. Sriwas ◽  
Pramod Kumar ◽  
R.K. Singh
Keyword(s):  
Code Rate ◽  
Length Variation ◽  
Constraint Length ◽  
Qualitative Performance

scholarly journals Automating Estimation of Battery State of Charge Using Experimental Data in MatLab

2020 ◽  
Vol 1 (4) ◽  
pp. 28-32
Author(s):  
Pradeep Vibhuti
Keyword(s):  
Experimental Data ◽  
The State ◽  
State Of Charge ◽  
Lookup Table ◽  
Governing Equations ◽  
Battery Voltage ◽  
Matlab Simulink ◽  
Look Up Table ◽  
Battery State Of Charge ◽  
Terminal Voltage

This paper explains how to estimate the state of charge (SOC) of a battery using implementation of characteristics governing equations and and lookup table. Look up table containing experimental data like charging resistance, discharging resistance and battery voltage in an excel sheet. Estimation of state of charge as a function of voltage is simulated with the help of experimental data in the form of lookup table in Matlab simulink and mscript. A 4V battery was charged and discharged at a 2.3 ampere for an hour. Matlab simulunk model with m.scipt is developed to determine terminal voltage and state of charge is obtained at any given time.

scholarly journals Performance of HIPERLAN/2 for 16QAM, with ¾ code rate with and without Rapp’s model

2011 ◽  
pp. 81-86
Author(s):  
Miss. Kiran Bondre ◽  
Mrs. Shubhangi Rathkanthiwar
Keyword(s):  
Power Amplifier ◽  
Code Rate ◽  
Transmission Channel ◽  
Matlab Simulink ◽  
Simulink Model ◽  
Simulink Simulation ◽  
Amplifier Model ◽  
Nonlinear Power Amplifier ◽  
Transmitted Signal ◽  
Pass Through

HIPERLAN/2 performance analysis via a MATLAB/Simulink simulation is present. This paper shows the results of simulations performed on a MATLAB/Simulink model HIPERLAN/2 system with and without a nonlinear power amplifier for AWGN channel. In the following analysis, an additive white Gaussian (AWGN) transmission channel is assumed since attention is focused on the effects on the nonlinearity. The power amplifier model used here is the Rapp’s Solid State Power Amplifier (SSPA) model. Here we showed that HIPERLAN/2 is much more sensitive to power amplifier nonlinearities. The paper shows that the received constellation points are considerably distorted after passing through the amplifier. The BER plot is more degraded when the transmitted signal passes through the amplifier than the plot when it does not pass through the amplifier.

scholarly journals A HARDWARE IMPLEMENTATION OF PUNGURED CONVOLUTIONAL CODES TO COMPLETE A VITERBI DECODER CORE

2005 ◽  
Vol 3 (02) ◽  
Author(s):  
E. Garda ◽  
M. Guzmán ◽  
D. Torres
Keyword(s):  
Large Scale ◽  
Convolutional Codes ◽  
Viterbi Decoder ◽  
Single Chip ◽  
Description Language ◽  
Large Scale Integration ◽  
Constraint Length ◽  
Hardware Description ◽  
Scale Integration ◽  
Convolutional Encoder

This paper presents a VLSI (Very Large Scale Integration) implementation of high punctured convolutional codes.We present a new circuit architecture that is capable of processing up to 10 convolutional codes rate (n-1)/n withthe constraint length-7 derived by the puncturing technique from the basic rate-1/2. The present circuit wasdesigned in order to complete an existing Viterbi decoder core, adding some extra functionality such as aconvolutional encoder, differential encoder/decoder, punctured convolutional encoder and symbol insertion todepuncture the received data. This extra functionality includes 10 different programmable coding rates without theneed to add additional logic in the system implementation, while other existing coders need it to attain highercoding rates. Therefore, a single chip solution is presented. The design was implemented in VHDL (Very High SpeedIntegrated Circuit Hardware Description Language) synthesized in Synopsys tool, and tested in a FPGA. Functionalverification was done, by means of simulation, to ensure that the circuit implements intended functionality. Suchsimulations were executed using Synopsys and a Sun Ultra Sparc 10 workstation. Different bit error probabilityperformance curves show an agreement between simulated and theoretical values.

scholarly journals POWER CONSUMPTION OPTIMIZATION IN REED SOLOMON ENCODERS OVER FPGA

2014 ◽  
Vol 44 (1) ◽  
pp. 81-85
Author(s):  
C. SANDOVAL
Keyword(s):  
Power Consumption ◽  
Design Method ◽  
Reconfigurable Hardware ◽  
Dynamic Power ◽  
Power Consumption Optimization

This paper presents an analysis of the Reed Solomon encoder model and GF (2m) multiplier component, with the aim of optimizing the power consumption for reconfigurable hardware. The methods used consisted of concatenation and reassignment circuit signals in the VHDL description. This treatment allowed achieving a reduction in the consumption of hardware resources and optimizing power consumption in the multiplier of 7.89%, which results in a reduction of the dynamic power of a 42.42% in the coder design optimized. With this development, it provides a design method with good performance, which can be applied to other circuits.

scholarly journals FPGA Implementation of Convolutional Encoder And Hard Decision Viterbi Decoder

2016 ◽  
pp. 126-130
Author(s):  
J. Tulasi ◽  
T.Venkata Lakshmi ◽  
M. Kamaraju
Keyword(s):  
Communication Systems ◽  
Block Codes ◽  
Viterbi Decoder ◽  
Space Communications ◽  
Convolutional Coding ◽  
Coding Scheme ◽  
Alternative Approach ◽  
Constraint Length ◽  
Convolutional Encoder ◽  
Digital Communication Systems

In this paper, we concern with designing and implementing a convolutional encoder and Viterbi decoder which are the essential block in digital communication systems using FPGA technology. Convolutional coding is a coding scheme used in communication systems including deep space communications and wireless communications. It provides an alternative approach to block codes for transmission over a noisy channel. The block codes can be applied only for the block of data. The convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.The motivation of this paper is to realize a Viterbi decoder having Constraint length 9 and code rate 1/2 by Xilinx 12.4i tools.

scholarly journals Integer-Only CNNs with 4 Bit Weights and Bit-Shift Quantization Scales at Full-Precision Accuracy

Electronics ◽  
2021 ◽  
Vol 10 (22) ◽  
pp. 2823
Author(s):  
Maarten Vandersteegen ◽  
Kristof Van Beeck ◽  
Toon Goedemé
Keyword(s):  
Neural Networks ◽  
High Precision ◽  
State Of The Art ◽  
Lookup Table ◽  
Memory Bandwidth ◽  
Quantization Scheme ◽  
Hardware Cost ◽  
Channel Quantization ◽  
Diverse Data ◽  
Hardware Platforms

Quantization of neural networks has been one of the most popular techniques to compress models for embedded (IoT) hardware platforms with highly constrained latency, storage, memory-bandwidth, and energy specifications. Limiting the number of bits per weight and activation has been the main focus in the literature. To avoid major degradation of accuracy, common quantization methods introduce additional scale factors to adapt the quantized values to the diverse data ranges, present in full-precision (floating-point) neural networks. These scales are usually kept in high precision, requiring the target compute engine to support a few high-precision multiplications, which is not desirable due to the larger hardware cost. Little effort has yet been invested in trying to avoid high-precision multipliers altogether, especially in combination with 4 bit weights. This work proposes a new quantization scheme, based on power-of-two quantization scales, that works on-par compared to uniform per-channel quantization with full-precision 32 bit quantization scales when using only 4 bit weights. This is done through the addition of a low-precision lookup-table that translates stored 4 bit weights into nonuniformly distributed 8 bit weights for internal computation. All our quantized ImageNet CNNs achieved or even exceeded the Top-1 accuracy of their full-precision counterparts, with ResNet18 exceeding its full-precision model by 0.35%. Our MobileNetV2 model achieved state-of-the-art performance with only a slight drop in accuracy of 0.51%.

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