scholarly journals Modeling and Simulation of Network-on-Chip Systems with DEVS and DEUS

2014 ◽  
Vol 2014 ◽  
pp. 1-9 ◽  
Author(s):  
Michele Amoretti
Keyword(s):  
Modeling And Simulation ◽  
Discrete Event ◽  
General Purpose ◽  
System Specification ◽  
Modeling Framework ◽  
Steep Learning Curve ◽  
Networks On Chip ◽  
Systems On Chip ◽  
Communication Architectures ◽  
On Chip

Networks on-chip (NoCs) provide enhanced performance, scalability, modularity, and design productivity as compared with previous communication architectures for VLSI systems on-chip (SoCs), such as buses and dedicated signal wires. Since the NoC design space is very large and high dimensional, evaluation methodologies rely heavily on analytical modeling and simulation. Unfortunately, there is no standard modeling framework. In this paper we illustrate how to design and evaluate NoCs by integrating the Discrete Event System Specification (DEVS) modeling framework and the simulation environment called DEUS. The advantage of such an approach is that both DEVS and DEUS support modularity—the former being a sound and complete modeling framework and the latter being an open, general-purpose platform, characterized by a steep learning curve and the possibility to simulate any system at any level of detail.

AN ANALYTICAL COMPARISON OF THE SPIDERGON AND RECTANGULAR MESH NoCs

2009 ◽  
Vol 10 (01n02) ◽  
pp. 167-188
Author(s):  
MAHMOUD MOADELI ◽  
ALI SHAHRABI ◽  
WIM VANDERBAUWHEDE ◽  
MOHAMED OULD-KHAOUA
Keyword(s):  
Discrete Event ◽  
Cost Effective ◽  
Network Throughput ◽  
Analytical Models ◽  
Networks On Chip ◽  
Mesh Topology ◽  
Systems On Chip ◽  
Rectangular Mesh ◽  
On Chip ◽  
Scalable Communication

Networks on chip (NoC) emerged as a structured and scalable communication medium for development of future Systems-on-Chip (SoC). Due to its unique features in terms of scalability and ease of synthesis, the (rectangular) mesh topology is regarded as an appropriate candidate for on-chip network development. On the other hand, the Spidergon NoC has been proposed as an alternative topology to realize cost effective multi-processor SoC (MPSoC) development. This paper presents analytical models of the average message latency and network throughput for both rectangular mesh and the Spidergon NoC employing wormhole switching. For each model, the validity of the analysis is verified by comparing the analytical model against the results produced by a discrete event simulator. Using the developed models, we then compare these topologies from different perspectives including manufacturing issues, message latency and network throughput.

scholarly journals A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 183
Author(s):  
Jose Ricardo Gomez-Rodriguez ◽  
Remberto Sandoval-Arechiga ◽  
Salvador Ibarra-Delgado ◽  
Viktor Ivan Rodriguez-Abdala ◽  
Jose Luis Vazquez-Avila ◽  
...  
Keyword(s):  
Single Chip ◽  
Synthesis Time ◽  
Networks On Chip ◽  
Data Dependencies ◽  
Layered Architecture ◽  
Systems On Chip ◽  
Challenges And Opportunities ◽  
Computing Platforms ◽  
On Chip ◽  
Many Core

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

scholarly journals Diseño e Implementación de un Multiprocessor Systems-on-Chip (MPSoC) Interconectado por una Networks-on-Chip (NoC)

MASKAY ◽  
2013 ◽  
Vol 3 (1) ◽  
pp. 40
Author(s):  
Wilson Mauricio Chicaiza ◽  
Daniel Gonzalo Verdesoto
Keyword(s):  
Multiprocessor Systems ◽  
Networks On Chip ◽  
Systems On Chip ◽  
On Chip ◽  
Medios De Comunicacion

En el presente documento se presenta una breve caracterización de los medios de comunicación empleados en arquitecturas multiprocesadas. Esta caracterización tiene como objetivo principal el mostrar un nuevo modelo de comunicación basado en conmutación de paquetes a los cuales se les denomina como Networks-On-Chip (NoC). Esta publicación muestra una arquitectura de red llamada NoC Hermes, la cual fue interconectada a un Multiprocessor-Systems-on-Chip (MPSoC) compuesto de cuatro procesadores MicroBlaze. Está conexión se la realizó gracias al diseño y desarrollo de una Interfaz de Red generada en código VHDL. Por medio de la Interfaz de Red se consiguió que los procesadores MicroBlaze interactúen con los Switches de Hermes a fin de crear una arquitectura multiprocesada interconectada por una NoC. Con el motivo de realizar comparaciones también se creó otra arquitectura de multiprocesadores interconectados por buses. Para ambas arquitecturas se desarrolló una aplicación de Esteganografía enla que existe multiprocesamiento de dos procesadores trabajando simultáneamente. Lamentablemente sobre dicha aplicación no fue posible medir directamente la latencia y el consumo de energía, razón por la cual se utilizó simuladores que permitieron estimar dichas mediciones.

Dynamically Reconfigurable Networks-on-Chip Using Runtime Adaptive Routers

2010 ◽  
pp. 28-66 ◽  
Author(s):  
Mário P. Véstias ◽  
Horácio C. Neto
Keyword(s):  
Quality Of Service ◽  
Power Consumption ◽  
First Generation ◽  
Networks On Chip ◽  
Dynamically Reconfigurable ◽  
Systems On Chip ◽  
High Bandwidth ◽  
Area Occupation ◽  
On Chip

The recent advances in IC technology have made it possible to implement systems with dozens or even hundreds of cores in a single chip. With such a large number of cores communicating with each other there is a strong pressure over the communication infrastructure to deliver high bandwidth, low latency, low power consumption and quality of service to guarantee real-time functionality. Networks-on-Chip are definitely becoming the only acceptable interconnection structure for today’s multiprocessor systems-on-chip (MPSoC). The first generation of NoC solutions considers a regular topology, typically a 2D mesh. Routers and network interfaces are mainly homogeneous so that they can be easily scaled up and modular design is facilitated. All advantages of a NoC infrastructure were proved with this first generation of NoC solutions. However, NoCs have a relative area and speed overhead. Application specific systems can benefit from heterogeneous communication infrastructures providing high bandwidth in a localized fashion where it is needed with improved area. The efficiency of both homogeneous and heterogeneous solutions can be improved if runtime changes are considered. Dynamically or runtime reconfigurable NoCs are the second generation of NoCs since they represent a new set of benefits in terms of area overhead, performance, power consumption, fault tolerance and quality of service compared to the previous generation where the architecture is decided at design time. This chapter discusses the static and runtime customization of routers and presents results with networks-on-chip with static and adaptive routers. Runtime adaptive techniques are analyzed and compared to each other in terms of area occupation and performance. The results and the discussion presented in this chapter show that dynamically adaptive routers are fundamental in the design of NoCs to satisfy the requirements of today’s systems-on-chip.

Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip

2005 ◽  
pp. 35-89 ◽  
Author(s):  
Theocharis Theocharides ◽  
Gregory M. Link ◽  
Narayanan Vijaykrishnan ◽  
Mary Jane Irwin
Keyword(s):  
Next Generation ◽  
Networks On Chip ◽  
Systems On Chip ◽  
On Chip

Discrete Event Modeling and Simulation of the Mythical Thought Morphodynamics Involved in Claude Levi Strauss Structural Analysis

2011 ◽  
pp. 152-178 ◽  
Author(s):  
Jean-François Santucci ◽  
Emmanuelle De Gentili ◽  
Ghjasippina Thury-Bouvet
Keyword(s):  
Modeling And Simulation ◽  
Discrete Event ◽  
Simulation Software ◽  
Oral Literature ◽  
System Specification ◽  
Discrete Event System Specification ◽  
Book Series ◽  
Event Modeling ◽  
Human And Social Sciences ◽  
Potential Benefits

In this chapter the authors present an exploration into the potential benefits of deploying structuralism analysis in the framework of human and social sciences using computer science modeling and simulation concepts and tools. They describe in detail in this chapter object oriented modeling and simulation software allowing the analysis of folktales. This software is based on the DEVS (Discrete Event System specification) formalism in order to both propose the modeling of a given myth issued from the oral literature of a given culture and the simulation of the corresponding myth transformations as described by Claude Levi Strauss when he dealt with mythical thought. The resulting software has been realized using the PythonDEVS kernel. The validation of the implemented software is performed on a set of folktales issued from corsican mythology and a set of myths from South and North America taken from Claude Levi Strauss’s Mythologiques book series.

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