scholarly journals Self-Passivation by Fluorine Plasma Treatment and Low-Temperature Annealing in SiGe Nanowires for Biochemical Sensors

2014 ◽  
Vol 2014 ◽  
pp. 1-7
Author(s):  
Kow-Ming Chang ◽  
Chiung-Hui Lai ◽  
Chu-Feng Chen ◽  
Po-Shen Kuo ◽  
Yi-Ming Chen ◽  
...  
Keyword(s):  
Low Temperature ◽  
Plasma Treatment ◽  
Oxide Layer ◽  
Field Effect Transistors ◽  
Chemical Species ◽  
Surface States ◽  
Hole Mobility ◽  
Oxide Semiconductor ◽  
Oxide Surface ◽  
Strained Si

Nanowires are widely used as highly sensitive sensors for electrical detection of biological and chemical species. Modifying the band structure of strained-Si metal-oxide-semiconductor field-effect transistors by applying the in-plane tensile strain reportedly improves electron and hole mobility. The oxidation-induced Ge condensation increases the Ge fraction in a SiGe-on-insulator (SGOI) and substantially increases hole mobility. However, oxidation increases the number of surface states, resulting in hole mobility degradation. In this work, 3-aminopropyltrimethoxysilane (APTMS) was used as a biochemical reagent. The hydroxyl molecule on the oxide surface was replaced by the methoxy groups of the APTMS molecule. We proposed a surface plasma treatment to improve the electrical properties of SiGe nanowires. Fluorine plasma treatment can result in enhanced rates of thermal oxidation and speed up the formation of a self-passivation oxide layer. Like a capping oxide layer, the self-passivation oxide layer reduces the rate of follow-up oxidation. Preoxidation treatment also improved the sensitivity of SiGe nanowires because the Si-F binding was held at a more stable interface state compared to bare nanowire on the SiGe surface. Additionally, the sensitivity can be further improved by either the N2 plasma posttreatment or the low-temperature postannealing due to the suppression of outdiffusion of Ge and F atoms from the SiGe nanowire surface.

Hole mobility enhancements in strained Si/Si1−yGey p-type metal-oxide-semiconductor field-effect transistors grown on relaxed Si1−xGex (x

2001 ◽  
Vol 79 (25) ◽  
pp. 4246-4248 ◽  
Author(s):  
C. W. Leitz ◽  
M. T. Currie ◽  
M. L. Lee ◽  
Z.-Y. Cheng ◽  
D. A. Antoniadis ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Hole Mobility ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Strained Si ◽  
P Type

Channel Engineering of SiGe-Based Heterostructures for High Mobility MOSFETs

2001 ◽  
Vol 686 ◽  
Author(s):  
Christopher W. Leitz ◽  
Matthew T. Currie ◽  
Minjoo L. Lee ◽  
Zhi-Yuan Cheng ◽  
Dimitri. A. Antoniadis ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
High Mobility ◽  
Hole Mobility ◽  
Oxide Semiconductor ◽  
Strained Si ◽  
Alloy Scattering ◽  
Dual Channel ◽  
Significant Performance ◽  
Performance Gains ◽  
Long Channel

AbstractStrained Si- and SiGe-based heterostructure metal-oxide-semiconductor field-effect transistors (MOSFETs) grown on relaxed SiGe virtual substrates exhibit dramatic electron and hole mobility enhancements over bulk Si, making them promising candidates for next generation complementary MOSFET (CMOS) devices. The most heavily investigated heterostructures consist of single strained Si layers grown upon relaxed SiGe substrates. While this configuration offers significant performance gains for both n- and p-MOSFETs, the enhanced hole mobility remains much lower than the enhanced electron mobility. By contrast, a combination of buried compressively strained Si1−yGey layers and tensile strained Si surface layers grown on relaxed Si1−xGex (x < y), hereafter referred to as dual channel heterostructures, offers nearly symmetric electron and hole mobilities without compromising n-MOSFET device performance. To investigate these heterostructures, we study the effects of alloy scattering on channel mobility in long channel MOSFETs. By using the combination of a buried Si0.2Ge0.8 channel and a strained Si surface channel grown on a relaxed Si0.5Ge0.5 virtual substrate, we have achieved nearly symmetric electron and hole mobility in the same heterostructure. By employing different virtual substrate compositions, we can decouple the effects of strain and alloy scattering in both tensile strained surface channels and compressively strained buried channels. We show that significant hole mobility enhancements can be achieved in dual channel heterostructures, even for buried channel compositions where alloy scattering is expected to be most severe. Furthermore, we show that alloy scattering in tensile strained SiGe surface channels impacts electrons much more severely than holes. Taken together, these results demonstrate that dual channel heterostructures can offer symmetric carrier mobilities and provide excellent performance gains for CMOS applications.

LOW TEMPERATURE MODELS OF METAL OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTORS

1995 ◽  
Vol 06 (02) ◽  
pp. 317-373 ◽  
Author(s):  
G. GILDENBLAT ◽  
D. FOTY
Keyword(s):  
Low Temperature ◽  
Field Effect Transistors ◽  
Numerical Models ◽  
Three Dimensional ◽  
Oxide Semiconductor ◽  
Characteristic Time Scale ◽  
Mos Transistors ◽  
Short Channel ◽  
Temperature Range ◽  
Dimensional Models

We review the modeling of silicon MOS devices in the 10–300 K temperature range with an emphasis on the specifics of low-temperature operation. Recently developed one-dimensional models of long-channel transistors are discussed in connection with experimental determination and verification of the effective channel mobility in a wide temperature range. We also present analytical pseudo-two-dimensional models of short-channel devices which have been proposed for potential use in circuit simulators. Several one-, two-, and three-dimensional numerical models are discussed in order to gain insight into the more subtle details of the low-temperature device physics of MOS transistors and capacitors. Particular attention is paid to freezeout effects which, depending on the device design and the ambient temperature range, may or may not be important for actual device operation. The numerical models are applied to study the characteristic time scale of freezeout transients in the space-charge regions of silicon devices, to the analysis and suppression of delayed turn-off in MOS transistors with compensated channel, and to the temperature dependence of three-dimensional effects in short-channel, narrow-channel MOSFETs.

The Effect of Strain on the Formation of Dislocations at the SiGe/Si Interface

MRS Bulletin ◽  
1996 ◽  
Vol 21 (4) ◽  
pp. 38-44 ◽  
Author(s):  
F.K. LeGoues
Keyword(s):  
Metal Oxide ◽  
High Speed ◽  
High Performance ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Design Rule ◽  
Strained Si

Recently much interest has been devoted to Si-based heteroepitaxy, and in particular, to the SiGe/Si system. This is mostly for economical reasons: Si-based technology is much more advanced, is widely available, and is cheaper than GaAs-based technology. SiGe opens the door to the exciting (and lucrative) area of Si-based high-performance devices, although optical applications are still limited to GaAs-based technology. Strained SiGe layers form the base of heterojunction bipolar transistors (HBTs), which are currently used in commercial high-speed analogue applications. They promise to be low-cost compared to their GaAs counterparts and give comparable performance in the 2-20-GHz regime. More recently we have started to investigate the use of relaxed SiGe layers, which opens the door to a wider range of application and to the use of SiGe in complementary metal oxide semiconductor (CMOS) devices, which comprise strained Si and SiGe layers. Some recent successes include record-breaking low-temperature electron mobility in modulation-doped layers where the mobility was found to be up to 50 times better than standard Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Even more recently, SiGe-basedp-type MOSFETS were built with oscillation frequency of up to 50 GHz, which is a new record, in anyp-type material for the same design rule.

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