scholarly journals Reversible Logic-Based Fault-Tolerant Nanocircuits in QCA

2013 ◽  
Vol 2013 ◽  
pp. 1-9 ◽  
Author(s):  
Bibhash Sen ◽  
Siddhant Ganeriwal ◽  
Biplab K. Sikdar
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Fault Tolerant ◽  
Digital Design ◽  
Quantum Cost ◽  
Quantum Dot Cellular Automata ◽  
Additional Cell ◽  
Potential Alternative ◽  
Fault Tolerant Systems ◽  
Reversible Alu

Parity-preserving reversible circuits are gaining importance for the development of fault-tolerant systems in nanotechnology. On the other hand, Quantum-dot Cellular Automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. This work targets design of reversible ALU (arithmetic logic unit) in QCA (Quantum-dot Cellular Automata) framework. The design is based on the fault tolerant reversible adders (FTRA) introduced in this paper. The proposed fault tolerant adder is a parity-preserving gate, and QCA implementation of FTRA achieved 47.38% fault-free output in the presence of all possible single missing/additional cell defects. The proposed designs are verified and evaluated over the existing ALU designs and found to be more efficient in terms of design complexity and quantum cost.

scholarly journals Design of Efficient Full Adder in Quantum-Dot Cellular Automata

2013 ◽  
Vol 2013 ◽  
pp. 1-10 ◽  
Author(s):  
Bibhash Sen ◽  
Ayush Rajoria ◽  
Biplab K. Sikdar
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Full Adder ◽  
Cmos Technology ◽  
Digital Design ◽  
Majority Gate ◽  
Feature Size ◽  
Quantum Dot Cellular Automata ◽  
Potential Alternative ◽  
High Level

Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. Quantum-dot cellular automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. Investigations on the reduction of QCA primitives (majority gates and inverters) for various adders are limited, and very few designs exist for reference. As a result, design of adders under QCA framework is gaining its importance in recent research. This work targets developing multi-layered full adder architecture in QCA framework based on five-input majority gate proposed here. A minimum clock zone (2 clock) with high compaction (0.01 μm2) for a full adder around QCA is achieved. Further, the usefulness of such design is established with the synthesis of high-level logic. Experimental results illustrate the significant improvements in design level in terms of circuit area, cell count, and clock compared to that of conventional design approaches.

Efficient design of reversible alu in quantum-dot cellular automata

Optik ◽  
2016 ◽  
Vol 127 (15) ◽  
pp. 6172-6182 ◽  
Author(s):  
Trailokya Nath Sasamal ◽  
Ashutosh Kumar Singh ◽  
Anand Mohan
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Efficient Design ◽  
Quantum Dot Cellular Automata ◽  
Reversible Alu

scholarly journals Design and Analysis of Fault-Tolerant 1:2 Demultiplexer Using Quantum-Dot Cellular Automata Nano-Technology

Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2565
Author(s):  
Saeid Seyedi ◽  
Nima Jafari Navimipour ◽  
Akira Otsuki
Keyword(s):  
Fault Tolerance ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Fault Tolerant ◽  
Nano Technology ◽  
Ultra Low Power ◽  
Quantum Dot Cellular Automata ◽  
Whole Process ◽  
Dislocation Cells ◽  
Rapid Switching

Quantum-dot Cellular Automata (QCA) is an innovative paradigm bringing hopeful applications in the perceptually novel computing layout in quantum electronics. The circuits manufactured by QCA technology can provide a notable decrease in size, rapid-switching velocity, and ultra-low power utilization. The demultiplexer is a beneficial component to optimize the whole process in any logical design, and therefore is very important in QCA. Moreover, fault-tolerant circuits can improve the reliability of digital circuits by redundancy. Hence, the present investigation illustrates a novel QCA-based fault-tolerant 1:2 demultiplexer construct that employs a two-input AND gate and inverter. The functionality of the suggested layout was executed and evaluated with the utilization of the QCADesigner 2.0.3 simulator. This paper utilizes cell redundancy on the wire, inverter, and AND gates for designing a fault-tolerant demultiplexer. Four components (i.e., missing cells, dislocation cells, extra cells, and misalignment) were analyzed by the QCADesigner simulator. The simulation results demonstrated that our proposed QCA-based fault-tolerant 1:2 demultiplexer acted more efficiently than prior constructs regarding delay and fault tolerance. The proposed fault-tolerant 1:2 demultiplexer could attain high fault-tolerance when single missing cell or extra cell faults exist in the QCA layout.

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