scholarly journals Synthesis of ZnO Nanoparticles to Fabricate a Mask-Free Thin-Film Transistor by Inkjet Printing

2012 ◽  
Vol 2012 ◽  
pp. 1-8 ◽  
Author(s):  
Chao-Te Liu ◽  
Wen-Hsi Lee ◽  
Tsu-Lang Shih
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Zno Nanoparticles ◽  
Inkjet Printing ◽  
Carrier Mobility ◽  
Gate Dielectric ◽  
Low Cost ◽  
Thin Film Transistor ◽  
Flexible Displays ◽  
Active Channel

We report a low-cost, mask-free, reduced material wastage, deposited technology using transparent, directly printable, air-stable semiconductor slurries and dielectric solutions. We have demonstrate an emerging process for fabricating printable transistors with ZnO nanoparticles as the active channel and poly(4-vinylphenol) (PVP) matrix as the gate dielectric, respectively, and the inkjet-printed ZnO TFTs have shown to exhibit the carrier mobility of 0.69 cm2/Vs and the threshold voltage of 25.5 V. We suggest that the printable materials and the printing technology enable the use of all-printed low-cost flexible displays and other transparent electronic applications.

scholarly journals Pentacene Active Channel Layers Prepared by Spin-Coating and Vacuum Evaporation Using Soluble Precursors for OFET Applications

2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
Shizuyasu Ochiai ◽  
Kumar Palanisamy ◽  
Santhakumar Kannappan ◽  
Paik-Kyun Shin
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Spin Coating ◽  
Dielectric Layer ◽  
Gate Dielectric ◽  
Low Cost ◽  
Vacuum Evaporation ◽  
Large Area ◽  
Process Technology ◽  
Active Channel

Pentacene OFETs of bottom-gate/bottom-contact were fabricated with three types of pentacene organic semiconductors and cross linked Poly(4-vinylphenol) or polycarbonate as gate dielectric layer. Two different processes were used to prepare the pentacene active channel layers: (1) spin-coating on dielectric layer using two different soluble pentacene precursors of SAP and DMP; (2) vacuum evaporation on PC insulator. X-ray diffraction studies revealed coexistence of thin film and bulk phase of pentacene from SAP and thin film phase of pentacene from DMP precursors. The field effect mobility of 0.031 cm2/Vs and threshold voltage of −12.5 V was obtained from OFETs fabricated from SAP precursor, however, the pentacene OFETs from DMP under same preparation yielded high mobility of 0.09 cm2/Vs and threshold value decreased to −5 V. It reflects that the mixed phase films had carrier mobilities inferior to films consisting solely of single phase. For comparison, we have also fabricated pentacene OFETs by vacuum evaporation on polycarbonate as the gate dielectric and obtained charge carrier mobilities as large as 0.62 cm2/Vs and threshold voltage of −8.5 V. We demonstrated that the spin-coated pentacene using soluble pentacene precursors could be alternative process technology for low cost, large area and low temperature fabrication of OFETs.

scholarly journals Effect of Novel Nanocomposite Materials for Enhancing Performance of Thin Film Transistor TFT Model

2016 ◽  
Vol 5 (1) ◽  
pp. 1
Author(s):  
Youssef Ahmed Mobarak ◽  
Moamen Atef
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Gate Dielectric ◽  
Low Cost ◽  
Thin Film Transistor ◽  
Analytical Models ◽  
Short Channel ◽  
High K ◽  
Wide Range ◽  
Low K

<span>The potential impact of high permittivity gate dielectrics on thin film transistors short channel and circuit performance has been studied using <a name="OLE_LINK110"></a><a name="OLE_LINK118"></a>highly accurate analytical models. In addition, the gate-to-channel capacitance and parasitic fringe capacitances have been extracted. The suggested model in this paper has been <a name="OLE_LINK37"></a><a name="OLE_LINK36"></a>increased the surface potential and decreased the <a name="OLE_LINK93"></a><a name="OLE_LINK92"></a>threshold voltage, whenever the conventional silicon dioxide gate dielectric<a name="OLE_LINK290"></a><a name="OLE_LINK280"></a> is replaced by high-K gate dielectric novel nanocomposite PVP/La<sub>2</sub>O<sub>3</sub>K<sub>ox</sub>=25. Also, it has been investigated that a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance, whenever the conventional silicon nitride is replaced by low-K gate sidewall spacer dielectric novel nanocomposite PTFE/SiO<sub>2</sub>K<sub>sp</sub>=2.9. Finally, it has been demonstrated that using low-K gate sidewalls with high-K gate insulators can be decreased the gate fringing field and threshold voltage. In addition, fabrication of nanocomposites from polymers and nano-oxide particles found to have potential candidates for using it in a wide range of applications in low cost due to low process temperature of these nanocomposites materials.</span>

scholarly journals Pentacene-Based Thin Film Transistor with Inkjet-Printed Nanocomposite High-K Dielectrics

2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
Chao-Te Liu ◽  
Wen-Hsi Lee ◽  
Jui-Feng Su
Keyword(s):  
Thin Film ◽  
Inkjet Printing ◽  
Gate Dielectric ◽  
Dielectric Film ◽  
Thin Film Transistor ◽  
Current Ratio ◽  
Large Current ◽  
High K ◽  
Dose Concentration ◽  
Top Contact

The nanocomposite gate insulating film of a pentacene-based thin film transistor was deposited by inkjet printing. In this study, utilizing the pearl miller to crumble the agglomerations and the dispersant to well stabilize the dispersion of nano-TiO2particles in the polymer matrix of the ink increases the dose concentration for pico-jetting, which could be as the gate dielectric film made by inkjet printing without the photography process. Finally, we realized top contact pentacene-TFTs and successfully accomplished the purpose of directly patternability and increase the performance of the device based on the nanocomposite by inkjet printing. These devices exhibited p-channel TFT characteristics with a high field-effect mobility (a saturation mobility of ̃0.58 cm2 V−1 s−1), a large current ratio (>103) and a low operation voltage (<6 V). Furthermore, we accorded the deposited mechanisms which caused the interface difference between of inkjet printing and spin coating. And we used XRD, SEM, Raman spectroscopy to help us analyze the transfer characteristics of pentacene films and the performance of OTFTs.

Threshold voltage control of a thin-film transistor using an Al–Zn–O channel prepared using atomic layer deposition by controlling the Al dopant positions

RSC Advances ◽  
2016 ◽  
Vol 6 (95) ◽  
pp. 92534-92540 ◽  
Author(s):  
Eom-Ji Kim ◽  
Won-Ho Lee ◽  
Sung-Min Yoon
Keyword(s):  
Thin Film ◽  
Atomic Layer Deposition ◽  
Threshold Voltage ◽  
Thin Film Transistor ◽  
Voltage Control ◽  
Atomic Layer ◽  
Layer Deposition ◽  
Doped Zno ◽  
Active Channel

We proposed a methodology for controlling the threshold voltage by adjusting the position of the Al dopant layer within an Al-doped-ZnO active channel of a thin film transistor.

A New Top Gate Pentacene Organic Thin Film Transistor Employing Vapor Deposited Polyimide as A Gate Dielectric

2006 ◽  
Vol 937 ◽  
Author(s):  
Chang-Wook Han ◽  
Sang-Geun Park ◽  
Chang-Yeon Kim ◽  
Min-Koo Han ◽  
Gun-Woo Hyung ◽  
...  
Keyword(s):  
Thin Film ◽  
Breakdown Voltage ◽  
Threshold Voltage ◽  
Gate Dielectric ◽  
Thin Film Transistor ◽  
Polyimide Film ◽  
Organic Thin Film ◽  
Organic Thin Film Transistor ◽  
Ft Ir

ABSTRACTA top gate pentacene TFT employing vapor deposited polyimide as a gate dielectric was fabricated. Polyimide was co-evaporated from 6FDA and ODA monomers and annealed at 150 °C in vacuum. The degree of imidization was verified by FT-IR. A breakdown voltage of 0.9 MV/cm of polyimide film was measured by MIM structure. A top gate pentacene TFT with W/L=25 has 0.01 cm2/Vs as a mobility, about 103 as an on-off ratio (In/off), −7.5V as a threshold voltage and 9 V per decade as a sub-threshold slope.

MODELING OF TRAPPING INDUCED THRESHOLD VOLTAGE SHIFT DEPENDENCY ON A TIME-VARYING GATE BIAS IN THIN-FILM TRANSISTORS

2012 ◽  
Vol 26 (23) ◽  
pp. 1250153
Author(s):  
TAEHO JUNG
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Discrete Model ◽  
Gate Dielectric ◽  
Thin Film Transistor ◽  
Charge Trapping ◽  
Time Varying ◽  
Threshold Voltage Shift ◽  
Exponential Time ◽  
Discrete States

The author has developed a discrete model for simulation to calculate the threshold voltage (VT) shift caused by charge trapping and detrapping in a thin film transistor (TFT) under a time-varying bias. The model divides continuous states into discrete states and simplifies tunneling among the discrete states to keep track of their occupancies. The simulation is carried out for a TFT that has traps in the gate dielectric uniformly distributed perpendicular to the semiconductor/dielectric interface and the results account for the stretched-exponential time dependence of VT shift.

Fabrication of a-Si:H Tfts at 120°C on Flexible Polyimide Substrates

1999 ◽  
Vol 558 ◽  
Author(s):  
Andrei Sazonov ◽  
Arokia Nathan ◽  
R.V.R. Murthy ◽  
S.G. Chamberlain
Keyword(s):  
Thin Film ◽  
Gate Dielectric ◽  
Low Cost ◽  
Thin Film Transistor ◽  
Performance Comparison ◽  
Hydrogen Gas ◽  
Large Area ◽  
Plastic Substrates ◽  
Glass Substrates ◽  
Contact Metallization

ABSTRACTThe fabrication of large-area thin-film transistor (TFT) arrays on thin flexible plastic substrates requires deposition of thin film layers at relatively low temperatures since the upper working temperature of low-cost plastic films should not exceed ∼200°C. In this paper, we report a fabrication process of a-Si:H TFTs at 120°C on flexible polyimide substrates for large-area imaging applications.Kapton HN (DuPont) films 50 and 125 μm thick and 3 inches in diameter, were used as substrates. Both sides of the polyimide substrate were first covered with 0.5 μm thick a-SiNx. The TFT structure includes: 120 nm thick room-temperature sputtered Al gate, 250 nm thick PECVD deposited a-SiNx for the gate dielectric, 50 nm thick a-Si:H deposited by PECVD from silane-hydrogen gas mixture, 50 nm thick n+ a-Si:H source- and drain contacts, and roomtemperature sputtered Al top contact metallization. We used dry etching for all layers except for the gate and top metal, which were patterned using wet etchants. For purpose of TFT performance comparison, Coming 7059 glass substrates were used.The performance of the fabricated TFT and its improvement with use of optimized a-Si:H and a-SiNx quality will be presented along with a discussion of the intrinsic mechanical stress in the thin film layers will also be discussed.

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