scholarly journals Designing High-Performance Fuzzy Controllers Combining IP Cores and Soft Processors

2012 ◽  
Vol 2012 ◽  
pp. 1-11 ◽  
Author(s):  
Oscar Montiel-Ross ◽  
Jorge Quiñones ◽  
Roberto Sepúlveda
Keyword(s):  
Parallel Programming ◽  
High Speed ◽  
High Performance ◽  
Hardware Description Language ◽  
System Response ◽  
Description Language ◽  
Tuning Method ◽  
Hardware Description ◽  
Ip Cores ◽  
Fuzzy Pd

This paper presents a methodology to integrate a fuzzy coprocessor described in VHDL (VHSIC Hardware Description Language) to a soft processor embedded into an FPGA, which increases the throughput of the whole system, since the controller uses parallelism at the circuitry level for high-speed-demanding applications, the rest of the application can be written in C/C++. We used the ARM 32-bit soft processor, which allows sequential and parallel programming. The FLC coprocessor incorporates a tuning method that allows to manipulate the system response. We show experimental results using a fuzzy PD+I controller as the embedded coprocessor.

scholarly journals SYNTHESIS AND FPGA–IMPLEMENTATION BASED NEURAL TECHNIQUE OF A NONLINEAR ADC MODEL

2014 ◽  
pp. 27-33
Author(s):  
Mounir Bouhedda ◽  
Mokhtar Attari
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Description Language ◽  
Description Language ◽  
Analog To Digital ◽  
Field Programmable ◽  
Hardware Description ◽  
Nonlinear Analog ◽  
Very High

The aim of this paper is to introduce a new architecture using Artificial Neural Networks (ANN) in designing a 6-bit nonlinear Analog to Digital Converter (ADC). A study was conducted to synthesise an optimal ANN in view to FPGA (Field Programmable Gate Array) implementation using Very High-speed Integrated Circuit Hardware Description Language (VHDL). Simulation and tests results are carried out to show the efficiency of the designed ANN.

scholarly journals Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library

VLSI Design ◽  
2000 ◽  
Vol 11 (4) ◽  
pp. 331-338 ◽  
Author(s):  
Chua-Chin Wang ◽  
Chenn-Jung Huang ◽  
I-Yen Chang
Keyword(s):  
High Speed ◽  
Hardware Description Language ◽  
Verilog Hdl ◽  
Description Language ◽  
Throughput Rate ◽  
Cell Library ◽  
Conversion Algorithm ◽  
Hardware Description ◽  
Simulation Results

A high speed 64b/32b integer divider employing digit-recurrence division method and the on-the-fly conversion algorithm, wherein a fast normalizer is included, which is used as the pre-processor of the proposed integer divider. For the sake of enhancing throughput rate, the proposed divider uses a mixed radix-8/4/2 division instead of the traditional radix-2 division. On-the-fly remainder adjustment is also realized in the converter module of the divider. The entire design is written in Verilog HDL (hardware description language) employing COMPASS 0.6 μm 1P3M cell library (V3.0), and then synthesized by SYNOPSYS. The simulation results indicate that our design is a better option than the existing long divider designs.

scholarly journals Space Vector Pulse Width Modulation for High-Speed Induction Motor Implemented in Nios II Softcore Processor

2018 ◽  
Vol 3 (1) ◽  
pp. 99-107
Author(s):  
Maciej Chojowski
Keyword(s):  
Induction Motor ◽  
Pulse Width ◽  
High Speed ◽  
Pulse Width Modulation ◽  
Classical Method ◽  
Hardware Description Language ◽  
Description Language ◽  
Space Vector ◽  
Nios Ii ◽  
Hardware Description

Abstract The purpose of the article was to present the idea of space vector pulse width modulation (SVPWM) and implementation in Nios II softcore processor. The SVPWM module was described in a classical method in hardware description language both as an independent structure and as an additional component to softcore processor. The available methods were compared, and the experiment was carried out in the laboratory to test implemented SVPWM algorithm using high-speed induction motor.

scholarly journals PERANCANGAN DAN IMPLEMENTASI ARSITEKTUR DEMAPPER 64-QAM DI FPGA

2017 ◽  
Author(s):  
Achmad Rizal Mauludin ◽  
Rina Pudji Astuti ◽  
Denny Darlis
Keyword(s):  
High Speed ◽  
Short Message Service ◽  
Hardware Description Language ◽  
Short Message ◽  
Least Significant Bit ◽  
Description Language ◽  
Error Process ◽  
Message Service ◽  
Hardware Description ◽  
Gate Array

Sistem telekomunikasi bertujuan untuk mengirimkan sinyal dari sumber informasi yang dapatberbentuk suara, pesan singkat atau Short Message Service (SMS), gambar, video dan layanan data ke tujuanyang diinginkan. Informasi yang akan dikirimkan akan diubah menjadi sinyal yang dapat dilewati mediatransmisi, dan agar sinyal yang diterima disisi penerima dapat dibaca, diperlukan demodulator yang dapatmengubah sinyal yang diterima menjadi informasi seperti yang dikirimkan. Demodulator 64-QuadratureAmplitude Modulation (QAM) adalah salah satu jenis demodulator yang mampu mendemodulasi sinyalfrekuensi tinggi.Dalam tugas akhir ini, telah dirancang dan diimplementasikan demapper 64-QAM yang merupakansub blok demodulator, pada FPGA (Field Programable Gate Array) yang menggunakan bahasa pengkodeanVery High Speed Integrated Cicuit (VHSIC) Hardware Description Language (VHDL) Fungsi dari blok iniadalah untuk memetakan balik simbol-simbol masukan dengan amplitudo dan fasa yang berbeda-beda yangsebelumnya telah direpresentasikan ke dalam bentuk bit-bit pada sisi pengirim. Pemetaan balik ini mengubahsimbol-simbol tersebut menjadi bit-bit informasi yang masih berupa bit-bit inphase dan quadrature.Dari hasil penelitian ini, untuk kondisi ideal atau gangguan didapatkan output di sisi penerima berupasebuah bit-bit informasi yang sama dengan bit-bit informasi yang dikirimkan pada sisi pengirim. Sedangkanuntuk kondisi ada gangguan, hasil outputnya masih sama dengan bit-bit informasi selama bit yang digangguadalah enam bit dari LSB (Least Significant bit), untuk tujuh bit yang diganggu error process yang terjadiadalah 21,8310 % sedangkan untuk empat belas bit yang diganggu error process yang terjadi sebesar 96,9072%.

scholarly journals Implementation of High Performance Microstepping Driver Using FPGA with the Aim of Realizing Accurate Control on a Linear Motion System

2013 ◽  
Vol 2013 ◽  
pp. 1-8
Author(s):  
Farid Alidoust Aghdam ◽  
Siamak Saeidi Haghi
Keyword(s):  
High Performance ◽  
Experimental Results ◽  
Hardware Description Language ◽  
Stepper Motor ◽  
Linear Motion ◽  
Description Language ◽  
Control Behavior ◽  
Motion System ◽  
Hardware Description ◽  
Hardware In Loop

This paper presents an FPGA-based microstepping driver which drives a linear motion system with a smooth and precise way. Proposed driver built on a Spartan3 FPGA (XC3S400 core) development board from Xilinx. Implementation of driver realized by an FPGA and using Verilog hardware description language in the Xilinx ISE environment. The driver’s control behavior can be adapted just by altering Verilog scripts. In addition, a linear motion system developed (with 4 mm movement per motor revolution) and coupled it to the stepper motor. The performance of the driver is tested by measuring the distance traveled on linear motion system. The experimental results verified using hardware-in-loop Matlab and Xilinx cosimulation method. This driver accomplishes a firm and accurate control and is responsive.

scholarly journals Support Vector Machine working on FPGA and the segmentation method of brain MR screening

2017 ◽  
Vol 4 (3) ◽  
pp. 120 ◽  
Author(s):  
Fatih Şişik ◽  
Eser Sert
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Description Language ◽  
Support Vector ◽  
Segmentation Method ◽  
Description Language ◽  
Field Programmable ◽  
Hardware Description ◽  
Very High

Alan Programlanabilir Kapı Dizileri (Field Programmable Gate Array-FPGA) programlanabilir sayısal bloklar ve bağlantılarını içeren cihazlar olup çok esnek ve hızlı çalışabilme özelliklerine sahiptir. Programlanabilen bu sayısal kapılar sayesinde karmaşık tasarımlar kolay bir şekilde geliştirilebilmektedir. FPGA’lar küçük boyutlarda olup bilgisayardan bağımsız mobil olarak ve bilgisayarlardan daha yüksek hızlarda çalışabilmektedirler. Veri madenciliğinin görevlerinden biri olan sınıflandırma probleminin çözümü için geliştirilmiş önemli makine öğrenimi algoritmalarından biri Destek Vektör Makineleri’ dir. Literatürde Destek Vektör Makineleri’ nin diğer birçok tekniğe göre daha başarılı sonuçlar verdiği kanıtlanmıştır. Tümör analizi, yüz tanıma, robotik göz oluşturma gibi konular, araştırmacıların görüntü işleme alanında yoğun olarak üzerinde çalıştıkları güncel, önemli ve zor problemlerden bazılarıdır. Bilgisayarda yapılan tümör analizinde, grafik ve resimlerin işlenmesinde yavaş işlem yapma ve aynı zamanda mobil olmama sorunlarından, FPGA donanımı ile görüntü işlemede bu sorunların üstesinden gelinmektedir. Bu çalışmada FPGA donanımında çalışan destek vektör makinası kullanılarak daha gerçekçi tümör analizi yapılarak tümörlü bölgelerin bulunması ve gerekli analiz sonuçlarının gösterilmesi amaçlanmaktadır. Böylece sağlık alanında da kullanılabilecek yararlı bir donanımın tasarımı gerçekleştirilecektir. Dolayısıyla gömülü sistemlerle anlatılan bu işlem süreçlerini gerçekleştiren çalışma sayısı çok az olduğundan çalışma özgün değer taşımaktadır. Buna ek olarak, FPGA’ ya özgü donanım tanımlama dillerinden biri olan Çok Yüksek Hızlı Tümleşik Devre Tanımlama Dili (Very High Speed Integrated Circuit  Hardware Description Language- VHDL) kullanılacaktır. Bölütleme sonucunun değerlendirilmesi için Uniformity Measure (UM) kullanılmıştır. UM değerlendirme sonucunun başarılı olduğu görülmüştür. Anahtar Kelimeler: Alan Programlanabilir Kapı Dizileri, FPGA, çok yüksek hızlı tümleşik devre tanımlama dili, vhdl, segmentasyon, destek vektör makinesi

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