scholarly journals Analysis and Design of Transformer-Based mm-Wave Transmit/Receive Switches

2012 ◽  
Vol 2012 ◽  
pp. 1-11 ◽  
Author(s):  
Ehsan Adabi ◽  
Ali M. Niknejad
Keyword(s):  
Insertion Loss ◽  
Input Power ◽  
Active Area ◽  
Cmos Process ◽  
Large Signal ◽  
Digital Cmos ◽  
Analysis And Design ◽  
Wave Transformer

Transformer-based shunt single pole, double-throw (SPDT) switches are analyzed, and design equations are provided. A mm-wave transformer-based SPDT shunt switch prototype was designed and fabricated in 90 nm digital CMOS process. It has a minimum insertion loss of 3.4 dB at 50 GHz from the single pole to the ON-thru port and a leakage of 19 dB from the single pole to the OFF-thru port. The isolation is 13.7 dB between the two thru ports. Large signal measurements verify that the switch is capable of handling +14 dBm of input power at its 1 dB compression point. The fabricated SPDT switch has a minute active area size of 60 μm×60 μm.

scholarly journals Analysis and Design of a Fully-Integrated High-Power Differential CMOS T/R Switch and Power Amplifier Using Multi-Section Impedance Transformation Technique

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1028
Author(s):  
Hyun-Woong Kim ◽  
Minsik Ahn ◽  
Ockgoo Lee ◽  
Hyoungsoo Kim ◽  
Hyungwook Kim ◽  
...  
Keyword(s):  
Insertion Loss ◽  
High Power ◽  
Cmos Process ◽  
Load Impedance ◽  
Power Differential ◽  
Analysis And Design ◽  
Power Added Efficiency ◽  
Front End ◽  
Power Handling Capability ◽  
Voltage Swing

In this paper, a new topology for a high-power single-pole-double-throw (SPDT) antenna switch is presented, and its loss mechanisms are fully analyzed. The differential architecture is employed in the proposed switch implementation to prevent unwanted channel formations of OFF-state Rx switch transistors by relieving the voltage swing over the Rx switch devices. In addition to that, the load impedance seen by the Tx switch is stepped down to reduce the voltage swing even more, allowing the antenna switch to handle a high-power signal without distortions. To drop the switch operating impedance, two matching networks are required at the input and the output of the Tx switch, respectively, and they are carefully implemented considering the integration issue of the front-end circuitries. From the loss analysis of the whole signal path, an optimum switch operating impedance is decided in view of a trade-off between power handling capability and insertion loss of the antenna switch. The insertion loss of the proposed design is compared to the conventional design with electromagnetic (EM) simulated transformer and inductors. The proposed antenna switch is implemented in a standard 0.18 µm CMOS process, and all switch devices adopt the deep n-well structure. The measured performance of the proposed transmitter front-end chain shows a 1 dB compression point (P1dB) of 32.1 dBm with 38.3% power-added efficiency (PAE) at 1.9 GHz.

A Fully Differential Variable Gain Amplifier for Portable Impedance Sensing Applications

2019 ◽  
Vol 7 ◽  
Author(s):  
Jorge Pérez Bailón ◽  
Jaime Ramírez-Angulo ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Active Area ◽  
Variable Gain Amplifier ◽  
Cmos Process ◽  
Current Steering ◽  
Impedance Sensing ◽  
Variable Gain ◽  
Fully Differential ◽  
Sensing Applications ◽  
Constant Bandwidth

This paper presents a Variable Gain Amplifier (VGA) designed in a 0.18 μm CMOS process to operate in an impedance sensing interface. Based on a transconductance-transimpedance (TC-TI) approach with intermediate analog-controlled current steering, it exhibits a gain ranging from 5 dB to 38 dB with a constant bandwidth around 318 kHz, a power consumption of 15.5 μW at a 1.8 V supply and an active area of 0.021 mm2.

scholarly journals NANO-studio, the design environment of filter banks implemented in standard CMOS technology

2021 ◽  
Author(s):  
Andrzej Handkiewicz ◽  
Mariusz Naumowicz
Keyword(s):  
Impulse Response ◽  
Filter Banks ◽  
Finite Impulse Response ◽  
Infinite Impulse Response ◽  
Cmos Process ◽  
Digital Cmos ◽  
Additional Advantage ◽  
Analysis And Synthesis ◽  
Optimization Parameters ◽  
Synthesis Filter

AbstractThe paper presents a method of optimizing frequency characteristics of filter banks in terms of their implementation in digital CMOS technologies in nanoscale. Usability of such filters is demonstrated by frequency-interleaved (FI) analog-to-digital converters (ADC). An analysis filter present in these converters was designed in switched-current technique. However, due to huge technological pitch of standard digital CMOS process in nanoscale, its characteristics substantially deviate from the required ones. NANO-studio environment presented in the paper allows adjustment, with transistor channel sizes as optimization parameters. The same environment is used at designing a digital synthesis filter, whereas optimization parameters are input and output conductances, gyration transconductances and capacitances of a prototype circuit. Transition between analog s and digital z domains is done by means of bilinear transformation. Assuming a lossless gyrator-capacitor (gC) multiport network as a prototype circuit, both for analysis and synthesis filter banks in FI ADC, is an implementation of the strategy to design filters with low sensitivity to parameter changes. An additional advantage is designing the synthesis filter as stable infinite impulse response (IIR) instead of commonly used finite impulse response (FIR) filters. It provides several dozen-fold saving in the number of applied multipliers.. The analysis and synthesis filters in FI ADC are implemented as filter pairs. An additional example of three-filter bank demonstrates versatility of NANO-studio software.

scholarly journals RF Small and large signal characterization of a 3D integrated GaN/RF-SOI SPST switch

2021 ◽  
pp. 1-6
Author(s):  
Frédéric Drillet ◽  
Jérôme Loraine ◽  
Hassan Saleh ◽  
Imene Lahbib ◽  
Brice Grandchamp ◽  
...  
Keyword(s):  
Power Level ◽  
Coplanar Waveguide ◽  
Average Power ◽  
Input Power ◽  
Capacitive Coupling ◽  
Rf Switch ◽  
Large Signal ◽  
Waveguide Transmission ◽  
Signal Characterization

Abstract This paper presents the radio frequency (RF) measurements of an SPST switch realized in gallium nitride (GaN)/RF-SOI technology compared to its GaN/silicon (Si) equivalent. The samples are built with an innovative 3D heterogeneous integration technique. The RF switch transistors are GaN-based and the substrate is RF-SOI. The insertion loss obtained is below 0.4 dB up to 30 GHz while being 1 dB lower than its GaN/Si equivalent. This difference comes from the vertical capacitive coupling reduction of the transistor to the substrate. This reduction is estimated to 59% based on a RC network model fitted to S-parameters measurements. In large signal, the linearity study of the substrate through coplanar waveguide transmission line characterization shows the reduction of the average power level of H2 and H3 of 30 dB up to 38 dBm of input power. The large signal characterization of the SPST shows no compression up to 38 dBm and the H2 and H3 rejection levels at 38 dBm are respectively, 68 and 75 dBc.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

Design Methodologies for Low-Power CMOS Operational Amplifiers in a 0.25¿m Digital CMOS Process

2006 ◽  
Author(s):  
Alfonso Cesar B. Albason ◽  
Neil Michael L. Axalan ◽  
Maria Theresa A. Gusad ◽  
John Richard E. Hizon ◽  
Marc D. Rosales
Keyword(s):  
Low Power ◽  
Operational Amplifiers ◽  
Cmos Process ◽  
Digital Cmos ◽  
Design Methodologies ◽  
Low Power Cmos ◽  
Cmos Operational Amplifiers

scholarly journals Transceiver with inductive coupling for wireless chip-to-chip communication using a 50-nm digital CMOS process

2013 ◽  
Vol 44 (9) ◽  
pp. 852-859 ◽  
Author(s):  
Changhyun Lee ◽  
Jonghoon Park ◽  
Jinho Yoo ◽  
Hyungjun Cho ◽  
Jungi Choi ◽  
...  
Keyword(s):  
Inductive Coupling ◽  
Cmos Process ◽  
Digital Cmos
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