Design Methodologies for Low-Power CMOS Operational Amplifiers in a 0.25¿m Digital CMOS Process

2006 ◽  
Author(s):  
Alfonso Cesar B. Albason ◽  
Neil Michael L. Axalan ◽  
Maria Theresa A. Gusad ◽  
John Richard E. Hizon ◽  
Marc D. Rosales
Keyword(s):  
Low Power ◽  
Operational Amplifiers ◽  
Cmos Process ◽  
Digital Cmos ◽  
Design Methodologies ◽  
Low Power Cmos ◽  
Cmos Operational Amplifiers

Optoelectronic CMOS Transistors: Performance Advantages for Sub-7nm ULSI, RF ASIC, Memories, and Power MOSFETs

MRS Advances ◽  
2019 ◽  
Vol 4 (48) ◽  
pp. 2585-2591
Author(s):  
James N. Pan
Keyword(s):  
Low Power ◽  
High Voltage ◽  
Series Resistance ◽  
Access Time ◽  
Cmos Process ◽  
Output Current ◽  
Process Flow ◽  
Power Mosfets ◽  
Cmos Transistors ◽  
Low Power Cmos

AbstractSubstantial increase of output current, and Ion / Ioff ratio for sub-7nm low power CMOS transistors, can be accomplished using a novel optoelectronic technology, which is 100% compatible with existing CMOS process flow. For RF or mixed signal ASICs, adding photonic components may improve the cut-off frequency, and reduce series resistance. Products that utilize power regulating devices, such as power MOSFETs, will benefit from the optoelectronic configuration to achieve much lower Rdson and high voltage at the same time. For semiconductor memories, such as DRAM or FLASH, the photonic technique may reduce the ERASE / WRITE / access time and improve the reliability.

Design and verification of a 10-bit 1.2-V 100-MSPS D/A IP core based on a 0.13-μm low power CMOS process

2010 ◽  
Vol 31 (9) ◽  
pp. 095007 ◽  
Author(s):  
Xu Bulu ◽  
Shao Bowen ◽  
Lin Xia ◽  
Yi Wei ◽  
Liu Yun
Keyword(s):  
Low Power ◽  
Cmos Process ◽  
Ip Core ◽  
Low Power Cmos

scholarly journals Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols

2019 ◽  
pp. 17-61 ◽  
Author(s):  
Utsav Banerjee ◽  
Tenzin S. Ukyab ◽  
Anantha P. Chandrakasan
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Energy Savings ◽  
Logic Gates ◽  
Public Key Cryptography ◽  
Building Blocks ◽  
Modular Arithmetic ◽  
Cmos Process ◽  
Order Of Magnitude ◽  
Low Power Cmos

Public key cryptography protocols, such as RSA and elliptic curve cryptography, will be rendered insecure by Shor’s algorithm when large-scale quantum computers are built. Cryptographers are working on quantum-resistant algorithms, and lattice-based cryptography has emerged as a prime candidate. However, high computational complexity of these algorithms makes it challenging to implement lattice-based protocols on low-power embedded devices. To address this challenge, we present Sapphire – a lattice cryptography processor with configurable parameters. Efficient sampling, with a SHA-3-based PRNG, provides two orders of magnitude energy savings; a single-port RAM-based number theoretic transform memory architecture is proposed, which provides 124k-gate area savings; while a low-power modular arithmetic unit accelerates polynomial computations. Our test chip was fabricated in TSMC 40nm low-power CMOS process, with the Sapphire cryptographic core occupying 0.28 mm2 area consisting of 106k logic gates and 40.25 KB SRAM. Sapphire can be programmed with custom instructions for polynomial arithmetic and sampling, and it is coupled with a low-power RISC-V micro-processor to demonstrate NIST Round 2 lattice-based CCA-secure key encapsulation and signature protocols Frodo, NewHope, qTESLA, CRYSTALS-Kyber and CRYSTALS-Dilithium, achieving up to an order of magnitude improvement in performance and energy-efficiency compared to state-of-the-art hardware implementations. All key building blocks of Sapphire are constant-time and secure against timing and simple power analysis side-channel attacks. We also discuss how masking-based DPA countermeasures can be implemented on the Sapphire core without any changes to the hardware.

Low-power CMOS LNA based on dual resistive-feedback structure with peaking inductor for wideband application

2013 ◽  
Vol 5 (1) ◽  
pp. 65-70 ◽  
Author(s):  
Meng-Ting Hsu ◽  
Shih-Yu Hsu ◽  
Yu-Hwa Lin
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Low Noise ◽  
Cmos Process ◽  
Output Stage ◽  
Chip Area ◽  
Inductive Peaking ◽  
Resistive Feedback ◽  
Low Power Cmos ◽  
Noise Amplifier

This paper presents a low-power and low-noise amplifier (LNA) with resistive-feedback configuration. The design consists of two resistive-feedback amplifiers. In order to reduce the chip area, a resistive-feedback inverter is adopted for input matching. The output stage adopts basic topology of an RC feedback for output matching, and adds two inductors for inductive peaking at the high band. The implemented LNA has a peak gain of 10.5 dB, the input reflection coefficient S11 is lower than −8 dB and the output reflection S22 is lower than −10.8 dB, and noise figure of 4.2–5.2 dB is between 1 and 10 GHz while consuming 12.65 mW from a 1.5 V supply. The chip area is only 0.69 mm2 and the figure of merit is 6.64 including the area estimation. The circuit was fabricated in a TSMC 0.18 um CMOS process.

Low Power CMOS Process Technologies and Characteristics for advanced High Density Mobile DRAM

2002 ◽  
Author(s):  
Chi Hoon Lee ◽  
Nam Hyuk Jo ◽  
Dong Gun Park ◽  
Duk Dong Kang ◽  
Dong-Ho Ahn ◽  
...  
Keyword(s):  
Low Power ◽  
High Density ◽  
Cmos Process ◽  
Low Power Cmos
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