scholarly journals Implementation of Ring-Oscillators-Based Physical Unclonable Functions with Independent Bits in the Response

2012 ◽  
Vol 2012 ◽  
pp. 1-13 ◽  
Author(s):  
Florent Bernard ◽  
Viktor Fischer ◽  
Crina Costea ◽  
Robert Fouquet
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Ring Oscillators ◽  
Physical Unclonable Functions ◽  
Precise Control ◽  
Placement And Routing ◽  
Unique Signature ◽  
Selection Of

The paper analyzes and proposes some enhancements of Ring-Oscillators-based Physical Unclonable Functions (PUFs). PUFs are used to extract a unique signature of an integrated circuit in order to authenticate a device and/or to generate a key. We show that designers of RO PUFs implemented in FPGAs need a precise control of placement and routing and an appropriate selection of ROs pairs to get independent bits in the PUF response. We provide a method to identify which comparisons are suitable when selecting pairs of ROs. Dealing with power consumption, we propose a simple improvement that reduces the consumption of the PUF published by Suh et al. in 2007 by up to 96.6%. Last but not least, we point out that ring oscillators significantly influence one another and can even be locked. This questions the reliability of the PUF and should be taken into account during the design.

Divergent synthesis of CF3-substituted polycyclic skeletons based on control of activation site of acid catalysts

2018 ◽  
Vol 54 (50) ◽  
pp. 6927-6930 ◽  
Author(s):  
Kazuma Yokoo ◽  
Keiji Mori
Keyword(s):  
Acid Catalysts ◽  
Precise Control ◽  
Selection Of ◽  
Activation Site

We report a divergent synthesis of CF3-substituted fused skeletons based on precise control of the activation site through the selection of acid catalysts.

scholarly journals Analysis and Suppression of Unwanted Turn-On and Parasitic Oscillation in SiC JFET-Based Bi-Directional Switches

Electronics ◽  
2018 ◽  
Vol 7 (8) ◽  
pp. 126 ◽  
Author(s):  
Lina Wang ◽  
Junyi Yang ◽  
Haobo Ma ◽  
Zeyuan Wang ◽  
Kabir Olanrewaju ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Matrix Converters ◽  
Turn On ◽  
High Efficient ◽  
Power Electronic Circuits ◽  
In Series ◽  
Ferrite Ring ◽  
Effect Transistor ◽  
Parasitic Oscillation ◽  
Selection Of

Silicon Carbide (SiC)-based Bi-Directional Switches (BDS) have great potential in the construction of several power electronic circuits including multi-level converters, solid-state breakers, matrix converters, HERIC (high efficient and reliable inverter concept) photovoltaic grid-connected inverters and so on. In this paper, two issues with the application of SiC-based BDSs, namely, unwanted turn-on and parasitic oscillation, are deeply investigated. To eliminate unwanted turn-on, it is proposed to add a capacitor (CX) paralleled at the signal input port of the driver IC (integrated circuit) and the capacitance range of CX is also analytically derived to guide the selection of CX. To mitigate parasitic oscillation, a combinational method, which combines a snubber capacitor (CJ) paralleled with the JFET (Junction Field Effect Transistor) and a ferrite ring connected in series with the power line, is proposed. It is verified that the use of CJ mainly improves the turn-off transient and the use of a ferrite ring damps the current oscillation during the turn-on transient significantly. The effects of the proposed methods have been demonstrated by theoretical analysis and verified by experimental results.

Servo respirator constructed from a positive-pressure ventilator

1976 ◽  
Vol 41 (2) ◽  
pp. 252-255 ◽  
Author(s):  
J. E. Remmers ◽  
H. Gautier
Keyword(s):  
Negative Feedback ◽  
Differential Amplifier ◽  
Positive Pressure ◽  
Precise Control ◽  
Pressure Signal ◽  
Response Characteristics ◽  
Tracheal Pressure ◽  
Selection Of

We have constructed an electronically controlled respirator from three commercially available components: a positive-pressure ventilator, a recorder pen motor, and a differential amplifier. Using negative feedback derived from a tracheal pressure signal, the instrument functions as a servo respirator which provides precise control of tracheal pressure. The system's power and response characteristics are well suited for ventilation of anesthetized cats and dogs. The servo respirator can be used as an externallycontrolled respiratory pump which provides flexibility in selection of the parameters of the ventilatory cycle. Alternatively, it can function as a “demand” respirator which generates transthoracic pressure proportional to efferent respiratory discharge.

scholarly journals Multi-Objective Cross-Layer Optimization for Selection of Cooperative Path Pairs in Multihop Wireless Ad hoc Networks

2013 ◽  
Vol 9 (3) ◽  
pp. 170 ◽  
Author(s):  
Nyoman Gunantara ◽  
Gamantyo Hendrantoro
Keyword(s):  
Power Consumption ◽  
Ad Hoc Networks ◽  
Wireless Ad Hoc Networks ◽  
Ad Hoc ◽  
Cross Layer ◽  
Multihop Wireless ◽  
Cross Layer Optimization ◽  
Hoc Networks ◽  
Pareto Method ◽  
Selection Of

This paper focuses in the selection of an optimal path pair for cooperative diversity based on cross-layer optimization in multihop wireless ad hoc networks. Cross-layer performance indicators, including power consumption, signal-to-noise ratio, and load variance are optimized using multi-objective optimization (MOO) with Pareto method. Consequently, optimization can be performed simultaneously to obtain a compromise among three resources over all possible path pairs. The Pareto method is further compared to the scalarization method in achieving fairness to each resource. We examine the statistics of power consumption, SNR, and load variance for both methods through simulations. In addition, the complexity of the optimization of both methods is evaluated based on the required computing time.

scholarly journals Backside Chippings Improvement through Wafer Dicing Parameter Optimization and Understanding the Anistropic Silicon Properties

2021 ◽  
pp. 144-152
Author(s):  
Aiza Marie E. Agudon ◽  
Bryan Christian S. Bacquian
Keyword(s):  
Integrated Circuit ◽  
Electronic Devices ◽  
Silicon Wafers ◽  
Form Complex ◽  
Work Related ◽  
Front End ◽  
Wafer Thickness ◽  
Fully Automatic ◽  
Direct Materials ◽  
Selection Of

Semiconductor Companies and Industries soar high as the trend for electronic gadgets and devices increases. Transition from “manual” to “fully automatic” application is one of the advantages why consumer adapt to changes and prefer electronic devices as one of daily answers. Individuals who admire these electronic devices often ask how they are made. As we look inside each device, we can notice interconnected microchips commonly called IC (Integrated Circuit). These are specially prepared silicon wafers where integrated circuit are developed. Commonly, each device is composed of numerous microchips depending on the design and functionality IC production is processed from “front-end” to “back-end” assembly. Front-end assembly includes wafer fabrication where electrical circuitry is prepared and integrated to every single silicon wafers. Back-end assembly covers processing the wafer by cutting into smaller individual and independent components called “dice”. Each dice will be placed into Leadframe, bonded with wires prior encapsulating with mold compounds. After molding, each IC will be cut through a process called singulation. Afterwards, all molded units are subjected for functional testing. Dice is central to each IC; it is where miniature transistor, resistor and capacitor are integrated to form complex small circuitry in microchips. Pre-assembly (Pre-assy) stations have the first hand prior to all succeeding stations. Live wafers are primary direct materials processed in these stations. Robust work instruction and parameter must be practiced during handling and processing to avoid gross rejection and possible work-related defects. The paper is all about the challenges to resolve and improved the backside chippings in 280um wafer thickness in mechanical dicing saw. The conventional Mechanical dicing process induce a lot of mechanical stress and vibration during the cutting process which oftentimes lead to backside chipping and die crack issues. However, backside chippings can mitigate with proper selection of parameter settings and understand the silicon wafer properties.

scholarly journals A New ALU Design using PNS-FCR: Static CMOS Logic for Microprocessors

2019 ◽  
Vol 8 (6S2) ◽  
pp. 876-882
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Design Methodology ◽  
Total Power ◽  
Data Path ◽  
Power Efficient ◽  
Efficient Data ◽  
Main Component ◽  
Static Logic ◽  
Important Design

Arithmetic Logic Unit (ALU) is the main component in the processors. Most important design consideration in integrated circuit is power. In all the components of ALU data path is the active one and it consumes more percent of power in the total power. In the modern microprocessors it is important to have power efficient data paths. To reduce the power consumption in microprocessors the ALU is designed using PNS-FCR static CMOS logic. In this paper static CMOS logic is used to reduce power consumption. Static technique does not need any clock. So it leads to less power consumption. For the implementation of the ALU with the PNS-FCR static logic mentor graphics tool is used. The power consumption of ALU is compared with and without using FCR. An 8-bit ALU is designed in mentor graphics with 130nm technology. The proposed design methodology gives less power consumption

scholarly journals Are trade-offs between flexibility and efficiency in systematic conservation planning avoidable ?

2019 ◽  
Author(s):  
Sabrine Drira ◽  
Frida Ben Rais Lasram ◽  
Tarek Hattab ◽  
Yunne Jai Shin ◽  
Amel Ben Rejeb Jenhani ◽  
...  
Keyword(s):  
Conservation Planning ◽  
Large Body ◽  
Efficient Solutions ◽  
Reserve Selection ◽  
Systematic Conservation Planning ◽  
Distribution Models ◽  
Precise Control ◽  
Trade Offs ◽  
Selection Framework ◽  
Selection Of

AbstractSpecies distribution models (SDMs) have been proposed as a way to provide robust inference about species-specific sites suitabilities, and have been increasingly used in systematic conservation planning (SCP) applications. However, despite the fact that the use of SDMs in SCP may raise some potential issues, conservation studies have overlooked to assess the implications of SDMs uncertainties. The integration of these uncertainties in conservation solutions requires the development of a reserve-selection approach based on a suitable optimization algorithm. A large body of research has shown that exact optimization algorithms give very precise control over the gap to optimality of conservation solutions. However, their major shortcoming is that they generate a single binary and indivisible solution. Therefore, they provide no flexibility in the implementation of conservation solutions by stakeholders. On the other hand, heuristic decision-support systems provide large amounts of sub-optimal solutions, and therefore more flexibility. This flexibility arises from the availability of many alternative and sub-optimal conservation solutions. The two principles of efficiency and flexibility are implicitly linked in conservation applications, with the most mathematically efficient solutions being inflexible and the flexible solutions provided by heuristics suffering sub-optimality. In order to avoid the trade-offs between flexibility and efficiency in systematic conservation planning, we propose in this paper a new reserve-selection framework based on mathematical programming optimization combined with a post-selection of SDM outputs. This approach leads to a reserve-selection framework that might provide flexibility while simultaneously addressing efficiency and representativeness of conservation solutions and the adequacy of conservation targets. To exemplify the approach we a nalyzed an experimental design crossing pre- and post-selection of SDM outputs versus heuristics and exact mathematical optimizations. We used the Mediterranean Sea as a biogeographical template for our analyses, integrating the outputs of 8 SDM techniques for 438 fishes species.

High-Performance Reconfigurable Computing

2019 ◽  
pp. 731-744
Author(s):  
Mário Pereira Vestias
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Reconfigurable Computing ◽  
High Performance ◽  
General Purpose ◽  
Reconfigurable Hardware ◽  
Coarse Grained ◽  
Lower Power ◽  
Fine Grained ◽  
Application Specific

High-performance reconfigurable computing systems integrate reconfigurable technology in the computing architecture to improve performance. Besides performance, reconfigurable hardware devices also achieve lower power consumption compared to general-purpose processors. Better performance and lower power consumption could be achieved using application-specific integrated circuit (ASIC) technology. However, ASICs are not reconfigurable, turning them application specific. Reconfigurable logic becomes a major advantage when hardware flexibility permits to speed up whatever the application with the same hardware module. The first and most common devices utilized for reconfigurable computing are fine-grained FPGAs with a large hardware flexibility. To reduce the performance and area overhead associated with the reconfigurability, coarse-grained reconfigurable solutions has been proposed as a way to achieve better performance and lower power consumption. In this chapter, the authors provide a description of reconfigurable hardware for high-performance computing.

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