scholarly journals Reduced-Precision Redundancy on FPGAs

2011 ◽  
Vol 2011 ◽  
pp. 1-12 ◽  
Author(s):  
Brian Pratt ◽  
Megan Fuller ◽  
Michael Wirthlin
Keyword(s):  
Digital Circuits ◽  
Fault Injection ◽  
Soft Error ◽  
Error Mitigation ◽  
Novel Method ◽  
Modular Redundancy ◽  
The Cost ◽  
Insight Into ◽  
Improve Reliability ◽  
Error Masking

Reduced-precision redundancy (RPR) has been shown to be a viable alternative to triple modular redundancy (TMR) for digital circuits. This paper builds on previous research by offering a detailed analysis of the implementation of RPR on FPGAs to improve reliability in soft error environments. Example implementations and fault injection experiments demonstrate the cost and benefits of RPR, showing how RPR can be used to improve the failure rate by up to 200 times over an unmitigated system at costs less than half that of TMR. A novel method is also presented for improving the error-masking ability of RPR by up to 5 times at no additional hardware cost under certain conditions. This research shows RPR to be a very flexible soft error mitigation technique and offers insight into its application on FPGAs.

scholarly journals Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial

Sensors ◽  
2021 ◽  
Vol 21 (4) ◽  
pp. 1392
Author(s):  
Óscar Ruano ◽  
Francisco García-Herrero ◽  
Luis Alberto Aranda ◽  
Alfonso Sánchez-Macián ◽  
Laura Rodriguez ◽  
...  
Keyword(s):  
Communication Systems ◽  
Finite Impulse Response ◽  
Fault Injection ◽  
Soft Error ◽  
Error Correction Codes ◽  
Classical Communication ◽  
Injection Process ◽  
Error Mitigation ◽  
Field Programmable ◽  
Modular Redundancy

Communication systems that work in jeopardized environments such as space are affected by soft errors that can cause malfunctions in the behavior of the circuits such as, for example, single event upsets (SEUs) or multiple bit upsets (MBUs). In order to avoid this erroneous functioning, this kind of systems are usually protected using redundant logic such as triple modular redundancy (TMR) or error correction codes (ECCs). After the implementation of the protected modules, the communication modules must be tested to assess the achieved reliability. These tests could be driven into accelerator facilities through ionization processes or they can be performed using fault injection tools based on software simulation such as the SEUs simulation tool (SST), or based on field-programmable gate array (FPGA) emulation like the one described in this work. In this paper, a tutorial for the setup of a fault injection emulation platform based on the Xilinx soft error mitigation (SEM) intellectual property (IP) controller is depicted step by step, showing a complete cycle. To illustrate this procedure, an online repository with a complete project and a step-by-step guide is provided, using as device under test a classical communication component such as a finite impulse response (FIR) filter. Finally, the integration of the automatic configuration memory error-injection (ACME) tool to speed up the fault injection process is explained in detail at the end of the paper.

A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code

2016 ◽  
Vol 8 (4) ◽  
pp. 65-68
Author(s):  
Swagata Mandal ◽  
Rourab Paul ◽  
Suman Sau ◽  
Amlan Chakrabarti ◽  
Subhasis Chattopadhyay
Keyword(s):  
Soft Error ◽  
Error Mitigation ◽  
Novel Method ◽  
Soft Error Mitigation

scholarly journals Fine-Grain Circuit Hardening Through VHDL Datatype Substitution

Electronics ◽  
2018 ◽  
Vol 8 (1) ◽  
pp. 24 ◽  
Author(s):  
Maria Muñoz-Quijada ◽  
Samuel Sanchez-Barea ◽  
Daniel Vela-Calderon ◽  
Hipolito Guzman-Miranda
Keyword(s):  
Radiation Effects ◽  
Digital Circuits ◽  
Fault Injection ◽  
Description Language ◽  
New Approach ◽  
Internal Memory ◽  
Fine Grain ◽  
Radiation Induced ◽  
Hardware Description ◽  
Modular Redundancy

Radiation effects can induce, amongst other phenomena, logic errors in digital circuits and systems. These logic errors corrupt the states of the internal memory elements of the circuits and can propagate to the primary outputs, affecting other onboard systems. In order to avoid this, Triple Modular Redundancy is typically used when full robustness against these phenomena is needed. When full triplication of the complete design is not required, selective hardening can be applied to the elements in which a radiation-induced upset is more likely to propagate to the main outputs of the circuit. The present paper describes a new approach for selectively hardening digital electronic circuits by design, which can be applied to digital designs described in the VHDL Hardware Description Language. When the designer changes the datatype of a signal or port to a hardened type, the necessary redundancy is automatically inserted. The automatically hardening features have been compiled into a VHDL package, and have been validated both in simulation and by means of fault injection.

SEU-SECURE PARITY PREDICTION MULTIPLIER ON SRAM-BASED FPGAs

2014 ◽  
Vol 23 (06) ◽  
pp. 1450081 ◽  
Author(s):  
REZA OMIDI GOSHEBLAGH ◽  
KARIM MOHAMMADI
Keyword(s):  
Field Programmable Gate Array ◽  
Fault Injection ◽  
Soft Error ◽  
Space Systems ◽  
Single Event ◽  
Single Event Upsets ◽  
Average Area ◽  
Error Mitigation ◽  
Field Programmable ◽  
Mitigation Techniques

Modern SRAM-based field programmable gate array (FPGA) devices offer high capability in implementing satellites and space systems. Unfortunately, these devices are extremely sensitive to various kinds of unwanted effects induced by space radiations especially single-event upsets (SEUs) as soft errors in configuration memory. To face this challenge, a variety of soft error mitigation techniques have been adopted in literature. In this paper, we describe an area-efficient multiplier architecture based on SRAM-FPGA that provides the self-checking capability against SEU faults. The proposed design approach, which is based on parity prediction, is able to concurrently detect the SEU faults. The implementation results of the proposed architecture reveal that the average area and delay overheads are respectively 25% and 34% in comparison with the plain version while the conventional duplication with comparison (DWC) architecture imposes 117% and 22% overheads. Moreover, the single and multi-upset fault injection experiments reveal that the proposed architecture averagely provides the failure coverage of 83% and 79% while the failure coverage of the duplicated structure is 85% and 84%, respectively for SEU and MEU faults.

scholarly journals Black Box Model based Self Healing Solution for Stuck at Faults in Digital Circuits

2017 ◽  
Vol 7 (5) ◽  
pp. 2451
Author(s):  
S. Meyyappan ◽  
V. Alamelumangai
Keyword(s):  
Digital Circuits ◽  
Fault Injection ◽  
Black Box ◽  
Self Healing ◽  
Combinational Circuit ◽  
True Nature ◽  
Area Overhead ◽  
Read Only Memory ◽  
Modular Redundancy ◽  
Injection Procedure

<p>The paper proposes a design strategy to retain the true nature of the output in the event of occurrence of stuck at faults at the interconnect levels of digital circuits. The procedure endeavours to design a combinational architecture which includes attributes to identify stuck at faults present in the intermediate lines and involves a healing mechanism to redress the same. The simulated fault injection procedure introduces both single as well as multiple stuck-at faults at the interconnect levels of a two level combinational circuit in accordance with the directives of a control signal. The inherent heal facility attached to the formulation enables to reach out the fault free output even in the presence of faults. The Modelsim based simulation results obtained for the Circuit Under Test [CUT] implemented using a Read Only Memory [ROM], proclaim the ability of the system to survive itself from the influence of faults. The comparison made with the traditional Triple Modular Redundancy [TMR] exhibits the superiority of the scheme in terms of fault coverage and area overhead.   </p>

Joint Effects of Aging and Process Variations on Soft Error Rate of Nano-Scale Digital Circuits

2020 ◽  
pp. 2150012
Author(s):  
Mohammad Sajjad Aghadadi ◽  
Mahdi Fazeli ◽  
Hakem Beitollahi
Keyword(s):  
Error Rate ◽  
Digital Circuits ◽  
Fault Injection ◽  
Process Variations ◽  
Aging Effect ◽  
Soft Error ◽  
Delay Model ◽  
Aging Effects ◽  
Soft Error Rate ◽  
Simulation Based

Soft errors have always been a concern in the design of digital circuits. As technology down-scales toward Nanometer sizes, emergence of aging effects, process variations, and Multiple Event Transients (METs) has made the soft error rate (SER) estimation of digital circuits very challenging. This paper intends to characterize the challenges by investigating the cross effects of theses issues in overall SER of a circuit. To this regard, we employ a simulation-based SER estimation approach in which the aging effect, process variations and METs are jointly considered in our fault injection process. In our simulation-based SER estimation approach, a statistical gate delay model is used. The fault injection results into ISCAS85 circuit benchmark reveal that the SER estimation without taking into account the aging effects, the process variations, and METs is significantly inaccurate.

BISS: A Built-In SEU Sensor for Soft Error Mitigation

2011 ◽  
Vol 130-134 ◽  
pp. 4228-4231 ◽  
Author(s):  
Zheng Feng Huang ◽  
Mao Xiang Yi
Keyword(s):  
Pulse Generator ◽  
Soft Errors ◽  
Performance Degradation ◽  
Soft Error ◽  
Digital Systems ◽  
Positive Pulse ◽  
Area Overhead ◽  
Error Mitigation ◽  
Soft Error Mitigation ◽  
The Cost

This paper presents a built-in SEU sensor (BISS) to detect soft errors in CMOS digital systems. BISS detects SEU-induced soft errors by monitoring the meta-stability in the flip-flops. BISS includes positive pulse generator, footed dynamic inverter and keeper. SPICE simulations validate the approach. Experiments show minor overhead in terms of area. BISS can yield 80% error coverage at the cost of 22% area overhead. As its prominent advantage, insertion of BISS will incur minimal performance degradation.

Locking down behavioural compliance: The role of emotion and emotion regulation in breaches of COVID-19 mitigation measures in Aotearoa New Zealand

2021 ◽  
pp. 135910532110299
Author(s):  
Terise Broodryk ◽  
Kealagh Robinson
Keyword(s):  
Public Health ◽  
Young Adults ◽  
New Zealand ◽  
Health Behaviours ◽  
Mitigation Measures ◽  
Aotearoa New Zealand ◽  
High Knowledge ◽  
The Cost ◽  
Insight Into

Although anxiety and worry can motivate engagement with COVID-19 preventative behaviours, people may cognitively reframe these unpleasant emotions, restoring wellbeing at the cost of public health behaviours. New Zealand young adults ( n = 278) experiencing nationwide COVID-19 lockdown reported their worry, anxiety, reappraisal and lockdown compliance. Despite high knowledge of lockdown policies, 92.5% of participants reported one or more policy breaches ( M  = 2.74, SD = 1.86). Counter to predictions, no relationships were found between anxiety or worry with reappraisal or lockdown breaches. Findings highlight the importance of targeting young adults in promoting lockdown compliance and offer further insight into the role of emotion during a pandemic.

scholarly journals Cost Analysis of a Novel Method for Ecological Compensation—A Study of the Translocation of Dead Wood

2021 ◽  
Vol 13 (11) ◽  
pp. 6075
Author(s):  
Ola Lindroos ◽  
Malin Söderlind ◽  
Joel Jensen ◽  
Joakim Hjältén
Keyword(s):  
Cost Efficiency ◽  
Dead Wood ◽  
Road Transportation ◽  
Ecological Value ◽  
Ecological Compensation ◽  
Work Time ◽  
Delivery Times ◽  
Novel Method ◽  
Cost Efficient ◽  
The Cost

Translocation of dead wood is a novel method for ecological compensation and restoration that could, potentially, provide a new important tool for biodiversity conservation. With this method, substrates that normally have long delivery times are instantly created in a compensation area, and ideally many of the associated dead wood dwelling organisms are translocated together with the substrates. However, to a large extent, there is a lack of knowledge about the cost efficiency of different methods of ecological compensation. Therefore, the costs for different parts of a translocation process and its dependency on some influencing factors were studied. The observed cost was 465 SEK per translocated log for the actual compensation measure, with an additional 349 SEK/log for work to enable evaluation of the translocation’s ecological results. Based on time studies, models were developed to predict required work time and costs for different transportation distances and load sizes. Those models indicated that short extraction and insertion distances for logs should be prioritized over road transportation distances to minimize costs. They also highlighted a trade-off between costs and time until a given ecological value is reached in the compensation area. The methodology used can contribute to more cost-efficient operations and, by doing so, increase the use of ecological compensation and the benefits from a given input.

Sign in / Sign up

Export Citation Format

Share Document