scholarly journals Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms

VLSI Design ◽  
2011 ◽  
Vol 2011 ◽  
pp. 1-9 ◽  
Author(s):  
I. Hameem Shanavas ◽  
Ramaswamy Kannan Gnanamurthy
Keyword(s):  
Local Search ◽  
Large Scale ◽  
Optimal Solution ◽  
Physical Design ◽  
Vlsi Circuit ◽  
Circuit Partitioning ◽  
Power Cost ◽  
Silicon Area ◽  
Minimum Delay ◽  
Scale Integration

Minimizing the wirelength plays an important role in physical design automation of very large-scale integration (VLSI) chips. The objective of wirelength minimization can be achieved by finding an optimal solution for VLSI physical design components like partitioning and floorplanning. In VLSI circuit partitioning, the problem of obtaining a minimum delay has prime importance. In VLSI circuit floorplanning, the problem of minimizing silicon area is also a hot issue. Reducing the minimum delay in partitioning and area in floorplanning helps to minimize the wirelength. The enhancements in partitioning and floorplanning have influence on other criteria like power, cost, clock speed, and so forth. Memetic Algorithm (MA) is an Evolutionary Algorithm that includes one or more local search phases within its evolutionary cycle to obtain the minimum wirelength by reducing delay in partitioning and by reducing area in floorplanning. MA applies some sort of local search for optimization of VLSI partitioning and floorplanning. The algorithm combines a hierarchical design technique like genetic algorithm and constructive technique like Simulated Annealing for local search to solve VLSI partitioning and floorplanning problem. MA can quickly produce optimal solutions for the popular benchmark.

scholarly journals Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

2014 ◽  
Vol 2014 ◽  
pp. 1-15 ◽  
Author(s):  
I. Hameem Shanavas ◽  
R. K. Gnanamurthy
Keyword(s):  
Genetic Algorithm ◽  
Evolutionary Algorithm ◽  
Design Automation ◽  
Large Scale ◽  
Hybrid Approach ◽  
Hybrid Genetic Algorithm ◽  
Optimal Solution ◽  
Physical Design ◽  
Silicon Area ◽  
Vlsi Physical Design

In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

Effective Memetic Algorithms for VLSI Design = Genetic Algorithms + Local Search + Multi-Level Clustering

2004 ◽  
Vol 12 (3) ◽  
pp. 327-353 ◽  
Author(s):  
Shawki Areibi ◽  
Zhen Yang
Keyword(s):  
Genetic Algorithms ◽  
Local Search ◽  
Optimization Problems ◽  
Memetic Algorithms ◽  
Vlsi Circuit ◽  
Circuit Partitioning ◽  
Placement Problem ◽  
Solution Quality ◽  
Combinatorial Optimization Problems ◽  
Cell Placement

Combining global and local search is a strategy used by many successful hybrid optimization approaches. Memetic Algorithms (MAs) are Evolutionary Algorithms (EAs) that apply some sort of local search to further improve the fitness of individuals in the population. Memetic Algorithms have been shown to be very effective in solving many hard combinatorial optimization problems. This paper provides a forum for identifying and exploring the key issues that affect the design and application of Memetic Algorithms. The approach combines a hierarchical design technique, Genetic Algorithms, constructive techniques and advanced local search to solve VLSI circuit layout in the form of circuit partitioning and placement. Results obtained indicate that Memetic Algorithms based on local search, clustering and good initial solutions improve solution quality on average by 35% for the VLSI circuit partitioning problem and 54% for the VLSI standard cell placement problem.

Rectilinear Steiner Tree Construction Techniques Using PB-SAT-Based Methodology

2019 ◽  
Vol 29 (04) ◽  
pp. 2050057
Author(s):  
Sudeshna Kundu ◽  
Suchismita Roy ◽  
Shyamapada Mukherjee
Keyword(s):  
Steiner Tree ◽  
Large Scale ◽  
Fundamental Problem ◽  
Physical Design ◽  
Steiner Tree Problem ◽  
Wire Length ◽  
Vlsi Physical Design ◽  
Rectilinear Steiner Tree ◽  
Large Scale Integration ◽  
Scale Integration

Rectilinear Steiner Tree (RST) construction is a fundamental problem in very large scale integration (VLSI) physical design. Its applications include placement and routing in VLSI physical design automation (PDA) where wire length and timing estimations for signal nets are obtained. In this paper, a pseudo-Boolean satisfiability (PB-SAT)-based approach is presented to solve rectilinear Steiner tree problem. But large nets are a bottleneck for any SAT-based approach. Hence, to deal with large nets, a region-partitioning-based algorithm is taken into consideration, which eventually achieves a reasonable running time. Furthermore, a clustering-based approach is also explored to improve the partitioning of nets by identifying clusters and then applying a heuristic-based approach to get the minimum wire length for each set of the clusters. Experimental results obtained by these techniques show that the proposed algorithm can solve the RST problem very effectively even on large circuits and it outperforms the widely used RST algorithm FLUTE with 3[Formula: see text][Formula: see text][Formula: see text]to 9[Formula: see text][Formula: see text][Formula: see text]speedups.

System-on-Chip Design of the Whirlpool Hash Function

2008 ◽  
pp. 256-270
Author(s):  
Paris Kitsos
Keyword(s):  
Hash Function ◽  
High Speed ◽  
Large Scale ◽  
System On Chip ◽  
Security Level ◽  
Chip Design ◽  
Silicon Area ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration

In this chapter, a system-on-chip design of the newest powerful standard in the hash families, named Whirlpool, is presented. With more details an architecture and two very large-scale integration (VLSI) implementations are presented. The first implementation is suitable for high speed applications while the second one is suitable for applications with constrained silicon area resources. The architecture permits a wide variety of implementation tradeoffs. Different implementations have been introduced and each specific application can choose the appropriate speed-area, trade-off implementation. The implementations are examined and compared in the security level and in the performance by using hardware terms. Whirlpool with RIPEMD, SHA-1, and SHA-2 hash functions are adopted by the International Organization for Standardization (ISO/IEC, 2003) 10118-3 standard. The Whirlpool implementations allow fast execution and effective substitution of any previous hash families’ implementations in any cryptography application.

scholarly journals Effective Usage of Chip Area by Optimizing the Dead Space

2019 ◽  
Vol 8 (6) ◽  
pp. 2601-2603
Keyword(s):  
Dead Space ◽  
Large Scale ◽  
Physical Design ◽  
Main Step ◽  
Floor Plan ◽  
Chip Area ◽  
Large Scale Integration ◽  
Area Optimization ◽  
The Dead ◽  
Scale Integration

In the modern VLSI (Very Large Scale Integration) physical design, floor plan is the main step to optimize the circuit. The objective of floor plan is to optimize the interconnection between modules, area optimization and minimize the dead space. For very deep micron technologies, one of the major issue to design an chip is Dead space in physical design. In this paper, we introduced an algorithm for reducing dead space. This algorithm wrote in tickel programming language and implemented in Cadence Innovas Encounter Tool. By comparing to default algorithm floor plan, this algorithm reduces more dead space in the floor plan stage of the design

Plant hormones, plant growth regulators

2014 ◽  
Vol 155 (26) ◽  
pp. 1011-1018 ◽  
Author(s):  
György Végvári ◽  
Edina Vidéki
Keyword(s):  
Nervous System ◽  
Growth And Development ◽  
Large Scale ◽  
Essential Role ◽  
Higher Plants ◽  
Structure And Function ◽  
Wide Sense ◽  
Large Scale Integration ◽  
Scale Integration ◽  
And Function

Plants seem to be rather defenceless, they are unable to do motion, have no nervous system or immune system unlike animals. Besides this, plants do have hormones, though these substances are produced not in glands. In view of their complexity they lagged behind animals, however, plant organisms show large scale integration in their structure and function. In higher plants, such as in animals, the intercellular communication is fulfilled through chemical messengers. These specific compounds in plants are called phytohormones, or in a wide sense, bioregulators. Even a small quantity of these endogenous organic compounds are able to regulate the operation, growth and development of higher plants, and keep the connection between cells, tissues and synergy beween organs. Since they do not have nervous and immume systems, phytohormones play essential role in plants’ life. Orv. Hetil., 2014, 155(26), 1011–1018.

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