scholarly journals Proposal of High-Temperature-Operation Tolerant SOI MOSFET and Preliminary Study on Device Performance Evaluation

2011 ◽  
Vol 2011 ◽  
pp. 1-8 ◽  
Author(s):  
Yasuhisa Omura
Keyword(s):  
Performance Evaluation ◽  
High Temperature ◽  
Band Gap ◽  
Threshold Voltage ◽  
Thermal Instability ◽  
Device Performance ◽  
Soi Mosfet ◽  
Preliminary Study ◽  
Simulation Results ◽  
High Temperature Operation

We propose a high-temperature-operation (HTOT) SOI MOSFET and show preliminary simulation results of its characteristics. It is demonstrated that HTOT SOI MOSFET operates safely at 700 K with no thermal instability because of its expanded effective bandgap. It is shown that its threshold voltage is higher than that of the conventional SOI MOSFET because its local thin Si regions offer an expanded effective band gap. It is shown that HTOT SOI MOSFET with 1-nm-thick local-thin Si regions is almost insensitive to temperature for (427 C). This confirms that HTOT SOI MOSFET is a promising device for future high-temperature applications.

1700V, 5.5mOhm-cm2 4H-SiC DMOSFET with Stable 225°C Operation

2014 ◽  
Vol 778-780 ◽  
pp. 903-906 ◽  
Author(s):  
Kevin Matocha ◽  
Kiran Chatty ◽  
Sujit Banerjee ◽  
Larry B. Rowland
Keyword(s):  
High Temperature ◽  
Temperature Stress ◽  
High Temperatures ◽  
Threshold Voltage ◽  
Room Temperature ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Device Reliability ◽  
Bias Temperature Stress ◽  
High Temperature Operation

We report a 1700V, 5.5mΩ-cm24H-SiC DMOSFET capable of 225°C operation. The specific on-resistance of the DMOSFET designed for 1200V applications is 8.8mΩ-cm2at 225°C, an increase of only 60% compared to the room temperature value. The low specific on-resistance at high temperatures enables a smaller die size for high temperature operation. Under a negative gate bias temperature stress (BTS) at VGS=-15 V at 225°C for 20 minutes, the devices show a threshold voltage shift of ΔVTH=-0.25 V demonstrating one of the key device reliability requirements for high temperature operation.

scholarly journals Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

2019 ◽  
Vol 2019 ◽  
pp. 1-12 ◽  
Author(s):  
Anjali Priya ◽  
Nilesh Anand Srivastava ◽  
Ram Awadh Mishra
Keyword(s):  
Threshold Voltage ◽  
Propagation Delay ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Gate Length ◽  
Metal Gate ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Silvaco Atlas

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

Electrical Characterization of Large Area 800 V Enhancement-Mode SiC VJFETs for High Temperature Applications

2009 ◽  
Vol 615-617 ◽  
pp. 715-718 ◽  
Author(s):  
Andrew Ritenour ◽  
Volodymyr Bondarenko ◽  
Robin L. Kelley ◽  
David C. Sheridan
Keyword(s):  
High Temperature ◽  
Elevated Temperature ◽  
Threshold Voltage ◽  
Room Temperature ◽  
Electrical Characterization ◽  
Saturation Current ◽  
Large Area ◽  
Enhancement Mode ◽  
High Temperature Operation

Prototype 800 V, 47 A enhancement-mode SiC VJFETs have been developed for high temperature operation (250 °C). With an active area of 23 mm2 and target threshold voltage of +1.25 V, these devices exhibited a 28 m room temperature on-resistance and excellent blocking characteristics at elevated temperature. With improved device packaging, on-resistance and saturation current values of 15 m and 100 A, respectively, are achievable.

scholarly journals Model Development for Threshold Voltage Stability Dependent on High Temperature Operations in Wide-Bandgap GaN-Based HEMT Power Devices

Micromachines ◽  
2018 ◽  
Vol 9 (12) ◽  
pp. 658 ◽  
Author(s):  
Huolin Huang ◽  
Feiyu Li ◽  
Zhonghao Sun ◽  
Yaqing Cao
Keyword(s):  
High Temperature ◽  
Analytical Model ◽  
Threshold Voltage ◽  
Computer Aided Design ◽  
Wide Bandgap ◽  
Physical Parameters ◽  
High Electron ◽  
Power Devices ◽  
Operation Condition ◽  
High Temperature Operation

Temperature-dependent threshold voltage (Vth) stability is a significant issue in the practical application of semi-conductor power devices, especially when they are undergoing a repeated high-temperature operation condition. The Vth analytical model and its stability are dependent on high-temperature operations in wide-bandgap gallium nitride (GaN)-based high electron mobility transistor (HEMT) devices that were investigated in this work. The temperature effects on the physical parameters—such as barrier height, conduction band, and polarization charge—were analysed to understand the mechanism of Vth stability. The Vth analytical model under high-temperature operation was then proposed and developed to study the measurement temperatures and repeated rounds dependent on Vth stability. The validity of the model was verified by comparing the theoretical calculation data with the experimental measurement and technology computer-aided design (TCAD) simulation results. This work provides an effective theoretical reference on the Vth stability of power devices in practical, high-temperature applications.

High-Temperature Operation of Photonic-Crystal Lasers for On-Chip Optical Interconnection

2012 ◽  
Vol E95.C (7) ◽  
pp. 1244-1251 ◽  
Author(s):  
Koji TAKEDA ◽  
Tomonari SATO ◽  
Takaaki KAKITSUKA ◽  
Akihiko SHINYA ◽  
Kengo NOZAKI ◽  
...  
Keyword(s):  
High Temperature ◽  
Photonic Crystal ◽  
Optical Interconnection ◽  
On Chip ◽  
High Temperature Operation

KUBOTA UCX

Alloy Digest ◽  
2008 ◽  
Vol 57 (6) ◽  
Keyword(s):  
Corrosion Resistance ◽  
High Temperature ◽  
Physical Properties ◽  
Tensile Properties ◽  
Temperature Performance ◽  
High Temperature Operation ◽  
Oxidation And Corrosion ◽  
Very High

Abstract Kubota UCX was developed for very high temperature operation for ethylene pyrolysis service. The alloy also has excellent oxidation and corrosion resistance. This datasheet provides information on composition, physical properties, elasticity, and tensile properties. It also includes information on high temperature performance and corrosion resistance as well as casting and joining. Filing Code: Ni-663. Producer or source: Kubota Metal Corporation, Fahramet Division.

An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

2019 ◽  
Vol 9 (4) ◽  
pp. 504-511
Author(s):  
Sikha Mishra ◽  
Urmila Bhanja ◽  
Guru Prasad Mishra
Keyword(s):  
Analytical Model ◽  
Surface Potential ◽  
Threshold Voltage ◽  
Silicon On Insulator ◽  
Junction Depth ◽  
Short Channel ◽  
Soi Mosfet ◽  
Minimum Surface ◽  
Recessed Channel ◽  
The Impact

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

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