scholarly journals Characterization of Series Resistance and Mobility Degradation Parameter and Optimizing Choice of Oxide Thickness in Thin OxideN-Channel MOSFET

2011 ◽  
Vol 2011 ◽  
pp. 1-4 ◽  
Author(s):  
Noureddine Maouhoub ◽  
Khalid Rais
Keyword(s):  
Series Resistance ◽  
Classical Model ◽  
Drain Current ◽  
Oxide Thickness ◽  
Exponential Model ◽  
Short Channel ◽  
Mobility Degradation ◽  
Strong Inversion ◽  
Roughness Amplitude ◽  
Two Parameters

We present two methods to extract the series resistance and the mobility degradation parameter in short-channel MOSFETs. The principle of the first method is based on the comparison between the exponential model and the classical model of effective mobility and for the second method is based on directly calculating the two parameters by solving a system of two equations obtained by using two different points in strong inversion at small drain bias from the characteristic (). The results obtained by these techniques have shown a better agreement with data measurements and allowed in the same time to determine the surface roughness amplitude and its influence on the maximum drain current and give the optimal oxide thickness.

scholarly journals Extraction of Series Resistance and Mobility Degradation in MOSFETs Using Iterative Method

2020 ◽  
Vol 5 (1) ◽  
pp. 21-27
Author(s):  
Noureddine Maouhoub ◽  
Khalid Rais
Keyword(s):  
Iterative Method ◽  
Series Resistance ◽  
Exponential Model ◽  
Short Channel ◽  
Attenuation Parameter ◽  
Low Field ◽  
Mobility Degradation ◽  
Strong Inversion ◽  
Roughness Amplitude ◽  
Good Agreement

Series resistance and mobility attenuation parameter are parasitic phenomena that limit the scaling of advanced MOSFETs. In this work, an iterative method is proposed to extract the series resistance and mobility degradation parameter in short channel MOSFETs. It also allows us to extract the surface roughness amplitude. The principle of this method is based on the exponential model of effective mobility and the least squares methods. From these, two analytical equations are obtained to determine the series resistance and the low field mobility as function of the mobility degradation. The mobility attenuation parameter is extracted using an iterative procedure to minimize the root means squared error (RMSE) value. The results obtained by this technique for a single short channel device have shown the good agreement with measurements data at strong inversion.  

scholarly journals Extraction of series resistance and mobility degradation parameter in MOSFETs using iterative method

2020 ◽  
Vol 1 (1) ◽  
pp. 26-31
Author(s):  
Noureddine Maouhoub ◽  
Khalid Rais
Keyword(s):  
Iterative Method ◽  
Series Resistance ◽  
Exponential Model ◽  
Short Channel ◽  
Attenuation Parameter ◽  
Low Field ◽  
Mobility Degradation ◽  
Strong Inversion ◽  
Roughness Amplitude ◽  
Good Agreement

Series resistance and mobility attenuation parameter are parasitic phenomena that limit the scaling of advanced MOSFETs. In this work, an iterative method is proposed to extract the series resistance and mobility degradation parameter in short channel MOSFETs. It also allows us to extract the surface roughness amplitude. The principle of this method is based on the exponential model of effective mobility and the least squares methods. From these, two analytical equations are obtained to determine the series resistance and the low field mobility as function of the mobility degradation. The mobility attenuation parameter is extracted using an iterative procedure to minimize the root means squared error (RMSE) value. The results obtained by this technique for a single short channel device have shown the good agreement with measurements data at strong inversion. 

An Analytical Drain Current Model for Dual-material Gate Graded - channel and Dual-oxide Thickness Cylindrical Gate (DMG-GC-DOT) MOSFET

2019 ◽  
Vol 9 (2) ◽  
pp. 291-297
Author(s):  
Hind Jaafar ◽  
Abdellah Aouaj ◽  
Ahmed Bouziane ◽  
Benjamin Iñiguez
Keyword(s):  
Current Model ◽  
Drain Current ◽  
Oxide Thickness ◽  
Subthreshold Current ◽  
The Poisson Equation ◽  
Strong Inversion ◽  
Cylindrical Form ◽  
Silvaco Atlas ◽  
Dual Material ◽  
Good Agreement

Background: A novel Dual Material Gate Graded Channel and Dual Oxide Thickness Cylindrical Gate (DMG-GC-DOT) MOSFET is presented in this paper. Methods: Analytical model of drain current is developed using a quasi-two-dimensional cylindrical form of the Poisson equation and is expressed as a function of the surface potential, which is calculated using the expressions of the current density. Results: Comparison of the analytical results with 3D numerical simulations using Silvaco Atlas - TCAD software presents a good agreement from subthreshold to strong inversion regime and for different bias voltages. Conclusion: Two oxide thicknesses with different permittivity can effectively improve the subthreshold current of DMG-GC-DOT MOSFET.

PHYSICS BASED ANALYTICAL MODELING OF NANOSCALE MULTIGATE MOSFETs

2013 ◽  
Vol 22 (01) ◽  
pp. 1350003 ◽  
Author(s):  
TOR A. FJELDLY ◽  
UDIT MONGA
Keyword(s):  
Potential Distribution ◽  
Drain Current ◽  
Capacitive Coupling ◽  
Thin Body ◽  
Scaling Effects ◽  
Modeling Framework ◽  
Short Channel ◽  
Strong Inversion ◽  
Symmetry Properties ◽  
Wide Range

Various physics based modeling schemes for multigate MOSFETs are presented. In all cases, the models are derived from an analysis of the device body electrostatics in terms of two- or three-dimensional Laplace's and Poisson's equations, where short-channel and scaling effects are implicitly accounted for. Thus a comprehensive modeling framework is derived for the subthreshold electrostatics of double-gate MOSFETs based on a conformal mapping analysis of the potential distribution in the device body arising from the inter-electrode capacitive coupling. This technique is also applied to the circular gate-all-around MOSFET by utilizing the symmetry properties of this device. For both these devices, the modeling is extended to include the strong inversion regime by a self-consistent procedure that simultaneously allows the calculation of the quasi-Fermi potential distribution, the drain current, and the intrinsic capacitances. In an alternative modeling framework, covering a wide range of multigate devices in a unified manner, the potential distribution is derived from a select set of isomorphic trial functions that reflect the geometry and symmetry properties of the devices. Modeling parameters used are self-consistently determined by imposing boundary conditions associated with Laplace's or Poisson's equation. Finally, the effects of quantum mechanical confinement are discussed for ultra thin body devices. The results of the modeling are in excellent agreement with numerical simulations.

scholarly journals S-curve Engineering for ON-state Performance using Anti-ferroelectric/Ferroelectric Stack Negative-Capacitance FinFET

2021 ◽  
Author(s):  
Shih-En Huang ◽  
Pin Su ◽  
Chenming Hu
Keyword(s):  
Series Resistance ◽  
Single Layer ◽  
Negative Capacitance ◽  
Gate Bias ◽  
Gate Stack ◽  
Short Channel ◽  
Ic Manufacturing ◽  
Strong Inversion ◽  
S Curve

<div>In this work, we report that the AFE/FE gate-stack can be utilized to engineer the S-curve for boosting the I<sub>ON</sub> of NC-FinFET. By using a short-channel BSIM-CMG compatible AFE/FE stack NC-FinFET model, the capacitance matching and ON-state performance for AFE/FE stack NC-FinFETs are investigated. Our study indicates that, the AFE/FE gate-stack can be used to improve the capacitance matching in strong inversion at higher gate-bias. Therefore, impressively higher ON-state current (compared to single-layer) can be achieved. In reality, source-drain series resistance will make such high IDS impractical. The more likely strategy is to use lower V<sub>DD</sub> to achieve much lower power consumption (and reduced vertical fields). While the transient NC effect also needs to be carefully investigated, this study suggests significant long term benefits to V<sub>DD</sub> scaling if materials with certain AFE and FE properties are developed and introduced in IC manufacturing in the future.</div>

scholarly journals S-curve Engineering for ON-state Performance using Anti-ferroelectric/Ferroelectric Stack Negative-Capacitance FinFET

2021 ◽  
Author(s):  
Shih-En Huang ◽  
Pin Su ◽  
Chenming Hu
Keyword(s):  
Series Resistance ◽  
Single Layer ◽  
Negative Capacitance ◽  
Gate Bias ◽  
Gate Stack ◽  
Short Channel ◽  
Ic Manufacturing ◽  
Strong Inversion ◽  
S Curve

<div>In this work, we report that the AFE/FE gate-stack can be utilized to engineer the S-curve for boosting the I<sub>ON</sub> of NC-FinFET. By using a short-channel BSIM-CMG compatible AFE/FE stack NC-FinFET model, the capacitance matching and ON-state performance for AFE/FE stack NC-FinFETs are investigated. Our study indicates that, the AFE/FE gate-stack can be used to improve the capacitance matching in strong inversion at higher gate-bias. Therefore, impressively higher ON-state current (compared to single-layer) can be achieved. In reality, source-drain series resistance will make such high IDS impractical. The more likely strategy is to use lower V<sub>DD</sub> to achieve much lower power consumption (and reduced vertical fields). While the transient NC effect also needs to be carefully investigated, this study suggests significant long term benefits to V<sub>DD</sub> scaling if materials with certain AFE and FE properties are developed and introduced in IC manufacturing in the future.</div>

scholarly journals Impact of device scaling on the electrical properties of MoS2 field-effect transistors

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Goutham Arutchelvan ◽  
Quentin Smets ◽  
Devin Verreck ◽  
Zubair Ahmed ◽  
Abhinav Gaur ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
Oxide Thickness ◽  
Channel Length ◽  
Contact Length ◽  
Power Performance ◽  
Semiconducting Materials ◽  
Large Area ◽  
Short Channel ◽  
Device Scaling ◽  
Performance Area

AbstractTwo-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices.

A method to extract mobility degradation and total series resistance of fully-depleted SOI MOSFETs

2002 ◽  
Vol 49 (1) ◽  
pp. 82-88 ◽  
Author(s):  
F.J.G. Sanchez ◽  
A. Ortiz-Conde ◽  
A. Cerdeira ◽  
M. Estrada ◽  
D. Flandre ◽  
...  
Keyword(s):  
Series Resistance ◽  
Fully Depleted ◽  
Mobility Degradation
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