Design of a Real-Time Face Detection Parallel Architecture Using High-Level Synthesis

2008 ◽  
Vol 2008 (1) ◽  
pp. 938256 ◽  
Author(s):  
Nicolas Farrugia ◽  
Franck Mamalet ◽  
Sébastien Roux ◽  
Fan Yang ◽  
Michel Paindavoine
Keyword(s):  
Real Time ◽  
Face Detection ◽  
Parallel Architecture ◽  
High Level Synthesis ◽  
High Level

AN EFFICIENT FPGA OVERLAY FOR COLOR TRANSFORMATION FUNCTION USING HIGH LEVEL SYNTHESIS

2021 ◽  
Vol 9 (1) ◽  
pp. 280-287
Author(s):  
Minal Deshmukh, Prasad Khandekar, Nishikant Sadafale
Keyword(s):  
Image Processing ◽  
Real Time ◽  
Transformation Function ◽  
High Level Synthesis ◽  
Smart Devices ◽  
Real Time Image Processing ◽  
Real Time Image ◽  
Color Transformation ◽  
High Level ◽  
Time Image

Image Processing is a significantly desirable in commercial, industrial, and medical applications. Processor based architectures are inappropriate for real time applications as Image processing algorithms are quite intensive in terms of computations. To reduce latency and limitation in performance due to limited amount of memory and fixed clock frequency for synthesis in processor-based architecture, FPGA can be used in smart devices for implementing real time image processing applications. To increase speed of real time image processing custom overlays (Hardware Library of programmable logic circuit) can be designed to run on FPGA fabric. The IP core generated by the HLS (High Level Synthesis) can be implemented on a reconfigurable platform which allows effective utilization of channel bandwidth and storage. In this paper we have presented FPGA overlay design for color transformation function using Xilinx’s python productivity board PYNQ-Z2 to get benefit in performance over a traditional processor. Performance comparison of custom overlay on FPGA and Processor based platform shows FPGA execution yields minimum computation time.

scholarly journals Exploration of FPGA-based electromagnetic transient real-time simulation system design using high-level synthesis

2019 ◽  
Vol 2019 (16) ◽  
pp. 1217-1220 ◽  
Author(s):  
Qiao Li ◽  
Yinxing Xiang ◽  
Qing Mu ◽  
Xing Zhang ◽  
Xiongfei Li ◽  
...  
Keyword(s):  
System Design ◽  
Real Time ◽  
Simulation System ◽  
High Level Synthesis ◽  
Real Time Simulation ◽  
Electromagnetic Transient ◽  
Time Simulation ◽  
High Level

A hardware implementation for real-time lane detection using high-level synthesis

2018 ◽  
Author(s):  
Chanon Khongprasongsiri ◽  
Pinit Kumhom ◽  
Watcharapan Suwansantisuk ◽  
Teerasak Chotikawanid ◽  
Surachate Chumpol ◽  
...  
Keyword(s):  
Real Time ◽  
Hardware Implementation ◽  
Lane Detection ◽  
High Level Synthesis ◽  
High Level

Accelerating Sobel Edge Detection Using Compressor Cells Over FPGAs

2018 ◽  
pp. 1133-1154
Author(s):  
Ahmed Abouelfarag ◽  
Marwa Ali Elshenawy ◽  
Esraa Alaaeldin Khattab
Keyword(s):  
Edge Detection ◽  
Real Time ◽  
Video Processing ◽  
High Level Synthesis ◽  
Computational Time ◽  
The Novel ◽  
Image And Video Processing ◽  
Sobel Edge Detection ◽  
High Level ◽  
Time Image

Recently, computer vision is playing an important role in many essential human-computer interactive applications, these applications are subject to a “real-time” constraint, and therefore it requires a fast and reliable computational system. Edge Detection is the most used approach for segmenting images based on changes in intensity. There are various kernels used to perform edge detection, such as: Sobel, Robert, and Prewitt, upon which, the most commonly used is Sobel. In this research a novel type of operator cells that perform addition is introduced to achieve computational acceleration. The novel operator cells have been employed in the chosen FPGA Zedboard which is well-suited for real-time image and video processing. Accelerating the Sobel edge detection technique is exploited using different tools such as the High-Level Synthesis tools provided by Vivado. This enhancement shows a significant improvement as it decreases the computational time by 26% compared to the conventional adder cells.

Accelerating Sobel Edge Detection Using Compressor Cells Over FPGAs

2017 ◽  
pp. 1-21
Author(s):  
Ahmed Abouelfarag ◽  
Marwa Ali Elshenawy ◽  
Esraa Alaaeldin Khattab
Keyword(s):  
Edge Detection ◽  
Real Time ◽  
Video Processing ◽  
High Level Synthesis ◽  
Computational Time ◽  
The Novel ◽  
Image And Video Processing ◽  
Sobel Edge Detection ◽  
High Level ◽  
Time Image

Recently, computer vision is playing an important role in many essential human-computer interactive applications, these applications are subject to a “real-time” constraint, and therefore it requires a fast and reliable computational system. Edge Detection is the most used approach for segmenting images based on changes in intensity. There are various kernels used to perform edge detection, such as: Sobel, Robert, and Prewitt, upon which, the most commonly used is Sobel. In this research a novel type of operator cells that perform addition is introduced to achieve computational acceleration. The novel operator cells have been employed in the chosen FPGA Zedboard which is well-suited for real-time image and video processing. Accelerating the Sobel edge detection technique is exploited using different tools such as the High-Level Synthesis tools provided by Vivado. This enhancement shows a significant improvement as it decreases the computational time by 26% compared to the conventional adder cells.

scholarly journals High-Level Synthesis of Online K-Means Clustering Hardware for a Real-Time Image Processing Pipeline

2019 ◽  
Vol 5 (3) ◽  
pp. 38 ◽  
Author(s):  
Aiman Badawi ◽  
Muhammad Bilal
Keyword(s):  
Image Processing ◽  
Image Segmentation ◽  
Real Time ◽  
Moving Average ◽  
Weighted Average ◽  
High Level Synthesis ◽  
Hardware Accelerator ◽  
Hardware Complexity ◽  
Processing Pipeline ◽  
High Level

The growing need for smart surveillance solutions requires that modern video capturing devices to be equipped with advance features, such as object detection, scene characterization, and event detection, etc. Image segmentation into various connected regions is a vital pre-processing step in these and other advanced computer vision algorithms. Thus, the inclusion of a hardware accelerator for this task in the conventional image processing pipeline inevitably reduces the workload for more advanced operations downstream. Moreover, design entry by using high-level synthesis tools is gaining popularity for the facilitation of system development under a rapid prototyping paradigm. To address these design requirements, we have developed a hardware accelerator for image segmentation, based on an online K-Means algorithm using a Simulink high-level synthesis tool. The developed hardware uses a standard pixel streaming protocol, and it can be readily inserted into any image processing pipeline as an Intellectual Property (IP) core on a Field Programmable Gate Array (FPGA). Furthermore, the proposed design reduces the hardware complexity of the conventional architectures by employing a weighted instead of a moving average to update the clusters. Experimental evidence has also been provided to demonstrate that the proposed weighted average-based approach yields better results than the conventional moving average on test video sequences. The synthesized hardware has been tested in real-time environment to process Full HD video at 26.5 fps, while the estimated dynamic power consumption is less than 90 mW on the Xilinx Zynq-7000 SOC.

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