High-Performance Timing-Driven Rank Filter
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This paper presents an FPGA implementation of a high-performance rank filter for video and image processing. The architecture exploits the features of current FPGAs and offers tradeoffs between complexity and performance. By maximizing the operating frequency, the complexity of the filter structure can be considerably reduced compared to previous 2D architectures.
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2008 ◽
Vol 56
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pp. 17-23
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2014 ◽
Vol 5
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pp. 61-74
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2009 ◽
Vol 1
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pp. 63-83
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1994 ◽
Vol 52
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pp. 940-941
2015 ◽
Vol E98.A
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pp. 1057_e1-1057_e1
2012 ◽
Vol 17
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pp. 207-216
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