Low level image processing operators on FPGA: implementation examples and performance evaluation

2002 ◽  
Author(s):  
M. Alves de Barros ◽  
M. Akil
Keyword(s):  
Image Processing ◽  
Performance Evaluation ◽  
Fpga Implementation ◽  
Low Level ◽  
And Performance

scholarly journals AN ASSOCIATIVE DATA PARALLEL COMPILATION MODEL FOR TIGHT INTEGRATION OF HIGH PERFORMANCE KNOWLEDGE RETRIEVAL AND COMPUTING

1994 ◽  
Vol 03 (01) ◽  
pp. 97-125 ◽  
Author(s):  
ARVIND K. BANSAL
Keyword(s):  
Performance Evaluation ◽  
High Performance ◽  
Loose Coupling ◽  
Abstract Machine ◽  
Data Movement ◽  
Left Hand ◽  
Low Level ◽  
Data Parallel ◽  
Data Alignment ◽  
And Performance

Associative Computation is characterized by intertwining of search by content and data parallel computation. An algebra for associative computation is described. A compilation based model and a novel abstract machine for associative logic programming are presented. The model uses loose coupling of left hand side of the program, treated as data, and right hand side of the program, treated as low level code. This representation achieves efficiency by associative computation and data alignment during goal reduction and during execution of low level abstract instructions. Data alignment reduces the overhead of data movement. Novel schemes for associative manipulation of aliased uninstantiated variables, data parallel goal reduction in the presence multiple occurrences of the same variables in a goal. The architecture, behavior, and performance evaluation of the model are presented.

scholarly journals High-Performance Timing-Driven Rank Filter

VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-6 ◽  
Author(s):  
Péter Szántó ◽  
Gábor Szedő ◽  
Béla Fehér
Keyword(s):  
Image Processing ◽  
High Performance ◽  
Fpga Implementation ◽  
Operating Frequency ◽  
Filter Structure ◽  
And Performance ◽  
Performance Timing

This paper presents an FPGA implementation of a high-performance rank filter for video and image processing. The architecture exploits the features of current FPGAs and offers tradeoffs between complexity and performance. By maximizing the operating frequency, the complexity of the filter structure can be considerably reduced compared to previous 2D architectures.

Design and Performance Evaluation of Image Processing Algorithms on GPUs

2011 ◽  
Vol 22 (1) ◽  
pp. 91-104 ◽  
Author(s):  
In Kyu Park ◽  
Nitin Singhal ◽  
Man Hee Lee ◽  
Sungdae Cho ◽  
Chris Kim
Keyword(s):  
Image Processing ◽  
Performance Evaluation ◽  
Image Processing Algorithms ◽  
Processing Algorithms ◽  
And Performance
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