scholarly journals Linear Approach for Synchronous State Stability in Fully Connected PLL Networks

2008 ◽  
Vol 2008 ◽  
pp. 1-13 ◽  
Author(s):  
José R. C. Piqueira ◽  
Maurízio Q. de Oliveira ◽  
Luiz H. A. Monteiro
Keyword(s):  
Integrated Circuits ◽  
Essential Feature ◽  
Taylor Series Expansion ◽  
Telecommunication Networks ◽  
Phase Locked Loops ◽  
Synchronous State ◽  
Manufacturing Automation ◽  
State Frequency ◽  
Distributed Solutions ◽  
Fully Connected

Synchronization is an essential feature for the use of digital systems in telecommunication networks, integrated circuits, and manufacturing automation. Formerly, master-slave (MS) architectures, with precise master clock generators sending signals to phase-locked loops (PLLs) working as slave oscillators, were considered the best solution. Nowadays, the development of wireless networks with dynamical connectivity and the increase of the size and the operation frequency of integrated circuits suggest that the distribution of clock signals could be more efficient if distributed solutions with fully connected oscillators are used. Here, fully connected networks with second-order PLLs as nodes are considered. In previous work, how the synchronous state frequency for this type of network depends on the node parameters and delays was studied and an expression for the long-term frequency was derived (Piqueira, 2006). Here, by taking the first term of the Taylor series expansion for the dynamical system description, it is shown that for a generic network withNnodes, the synchronous state is locally asymptotically stable.

scholarly journals Fully Connected PLL Networks: How Filter Determines the Number of Nodes

2009 ◽  
Vol 2009 ◽  
pp. 1-13 ◽  
Author(s):  
Átila Madureira Bueno ◽  
André Alves Ferreira ◽  
José Roberto C. Piqueira
Keyword(s):  
Integrated Circuits ◽  
Distribution Systems ◽  
Second Order ◽  
Phase Locked Loops ◽  
Clock Distribution ◽  
Synchronous State ◽  
First Order ◽  
Automation Systems ◽  
Low Pass ◽  
Fully Connected

Synchronization plays an important role in telecommunication systems, integrated circuits, and automation systems. Formerly, the masterslave synchronization strategy was used in the great majority of cases due to its reliability and simplicity. Recently, with the wireless networks development, and with the increase of the operation frequency of integrated circuits, the decentralized clock distribution strategies are gaining importance. Consequently, fully connected clock distribution systems with nodes composed of phase-locked loops (PLLs) appear as a convenient engineering solution. In this work, the stability of the synchronous state of these networks is studied in two relevant situations: when the node filters are first-order lag-lead low-pass or when the node filters are second-order low-pass. For first- order filters, the synchronous state of the network shows to be stable for any number of nodes. For second-order filter, there is a superior limit for the number of nodes, depending on the PLL parameters.

scholarly journals Synchronous state in a fully connected phase-locked loop network

2006 ◽  
Vol 2006 ◽  
pp. 1-12 ◽  
Author(s):  
J. R. C. Piqueira ◽  
M. Q. Oliveira ◽  
L. H. A. Monteiro
Keyword(s):  
Steady State ◽  
Dynamic Process ◽  
Numerical Experiments ◽  
Phase Locked Loops ◽  
Synchronous State ◽  
Propagation Delays ◽  
Node Network ◽  
Loop Network ◽  
Free Running ◽  
Fully Connected

Fully connected phase-locked networks are built with all nodes exchanging phase and frequency signals. The nodes are phase-locked loops (PLLs) with slightly different free-running frequencies. The synchronous state emerges from a dynamic process with the phase interactions generating a common frequency steady state. In this work, an estimation is analytically obtained for the synchronous state in a genericN-node network. Numerical experiments complete the analysis of the fully connected network relating free-running frequencies, node gains, and propagation delays.

scholarly journals On-chip continuous-variable quantum entanglement

Nanophotonics ◽  
2016 ◽  
Vol 5 (3) ◽  
pp. 469-482 ◽  
Author(s):  
Genta Masada ◽  
Akira Furusawa
Keyword(s):  
Quantum Information ◽  
Integrated Circuits ◽  
Quantum Entanglement ◽  
Information Science ◽  
Essential Feature ◽  
Continuous Variable ◽  
Entangled State ◽  
Discrete Variable ◽  
Light Beams ◽  
Optical Circuits

AbstractEntanglement is an essential feature of quantum theory and the core of the majority of quantum information science and technologies. Quantum computing is one of the most important fruits of quantum entanglement and requires not only a bipartite entangled state but also more complicated multipartite entanglement. In previous experimental works to demonstrate various entanglement-based quantum information processing, light has been extensively used. Experiments utilizing such a complicated state need highly complex optical circuits to propagate optical beams and a high level of spatial interference between different light beams to generate quantum entanglement or to efficiently perform balanced homodyne measurement. Current experiments have been performed in conventional free-space optics with large numbers of optical components and a relatively large-sized optical setup. Therefore, they are limited in stability and scalability. Integrated photonics offer new tools and additional capabilities for manipulating light in quantum information technology. Owing to integrated waveguide circuits, it is possible to stabilize and miniaturize complex optical circuits and achieve high interference of light beams. The integrated circuits have been firstly developed for discrete-variable systems and then applied to continuous-variable systems. In this article, we review the currently developed scheme for generation and verification of continuous-variable quantum entanglement such as Einstein-Podolsky-Rosen beams using a photonic chip where waveguide circuits are integrated. This includes balanced homodyne measurement of a squeezed state of light. As a simple example, we also review an experiment for generating discrete-variable quantum entanglement using integrated waveguide circuits.

500 kHz – 5 MHz Phase-Locked Loops in High-Temperature Silicon Carbide CMOS

2014 ◽  
Vol 2014 (HITEC) ◽  
pp. 000076-000083 ◽  
Author(s):  
Paul Shepherd ◽  
Ashfaqur Rahman ◽  
Shamim Ahmed ◽  
A Matt Francis ◽  
Jim Holmes ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Integrated Circuits ◽  
Extreme Environments ◽  
Phase Locked Loops ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Fully Integrated ◽  
Improved Performance

Silicon Carbide (SiC) integrated circuits processes show promise for improved performance in high temperature, high radiation, and other extreme environments. The circuits described are the first implementations of phase-locked or delay-locked loops in SiC. The PLL utilizes a common charge-pump topology including a fully integrated passive loop filter, and were designed with a target maximum operating frequency of 5 MHz. Component blocks use novel topologies to optimize performance in a SiC CMOS process. Experimental results of both the complete PLL as well as the Phase Frequency Detector and Voltage Controlled Oscillator components are presented. Operation of the PLL at frequencies up to 1.5 MHz is demonstrated through test results of unpackaged die.

scholarly journals THE ASSESS THE FAULT-TOLERANCE, EFFİCİENCY AND PERFORMANCE OF MİLİTARY FİELD LOCAL NETWORK TOPOLOGY

2021 ◽  
Vol 5 (3) ◽  
pp. 81-85
Author(s):  
Ardil Ramazan Nastakalov
Keyword(s):  
Fault Tolerance ◽  
Network Topology ◽  
Telecommunication Networks ◽  
Local Network ◽  
Network Stability ◽  
Mathematical Methods ◽  
High Power Consumption ◽  
Low Efficiency ◽  
And Performance ◽  
Fully Connected

Depending on the location of communication nodes of the control points and points of relay in the field, especially in mountainous areas, finding line of sight (LOS) and establishing a good radio relay connection can be challenging. In addition, depending on the requirements for bandwidth and communication stability, in the field, a situation often arises where it is possible to build a network only based on certain types of topologies. To assess the security of military field telecommunication networks, it is important to determine such important parameters as network stability or fault-tolerance, efficiency, transmission capacity and delay time. It is known that the greatest values of these parameters are achieved in the type of "fully connected" network topology. However, low efficiency, high power consumption, difficulties in safely and hidden placement of a large number of vehicles in the battle area and the complexity of maintenance, as well as the fact that radio relay hardware vehicles consist mainly of 2 sets of radio relay devices make this type of topology unsuitable for field networks. Therefore, it is important to define a network topology with high stability, using the minimum amount of radio relay vehicles. For the above reason, the article proposes mathematical methods for calculating the fault tolerance and efficiency of the selected network topology, as well as fault tolerance, bandwidth and latency for each network node.

Comparing LQG/LTR and the SDRE Techniques for Hybrid Fully-Connected PLL Network Control

2013 ◽  
Author(s):  
Átila Madureira Bueno ◽  
Angelo Marcelo Tusset ◽  
Diego Paolo Ferruzzo Correa ◽  
José Roberto Castilho Piqueira ◽  
José Manoel Balthazar
Keyword(s):  
Integrated Circuits ◽  
Network Control ◽  
Clock Signal ◽  
Clock Distribution ◽  
Signal Distribution ◽  
Performance Requirements ◽  
Distribution Process ◽  
And Performance ◽  
The Stability ◽  
Fully Connected

Synchronization plays an important role in telecommunication systems and integrated circuits. The Master-Slave is a commonly used strategy for clock signal distribution. However, due to the wireless networks development and the higher operation frequency of integrated circuits, the Mutually-Connected clock distribution strategies are becoming important, and the Fully-Connected strategy appears as a convenient engineering solution. The main drawback of the Fully-Connected architecture is the definition of control algorithms that assure the stability of the network sinchronization. In hybrid synchronization techniques groups of nodes synchronized by the Fully-Connected architecture are synchronized with network master clocks by using the Master-Slave tecnique. In this arrangement, if a route of clock signal distribution becomes inoperative, the group of Fully-Connected nodes retain for some time the original phase and frequency received from the network. The Fully-Connected architecture complexity imposes difficulties to satisfy both stability and performance requirements in the control system design. For that reason the multi-variable LQG/LTR and the SDRE control techniques are applied in order to fulfill both stability and performance requirements. The performance of both techniques are compared, and the results seems to confirm the improvement in the transient response and in the precision of the clock distribution process.

SYNCHRONIZATION OF CROSS-WELL CHAOS IN COUPLED DUFFING OSCILLATORS

2005 ◽  
Vol 19 (20) ◽  
pp. 3205-3216 ◽  
Author(s):  
U. E. VINCENT ◽  
A. N. NJAH ◽  
O. AKINLADE ◽  
A. R. T. SOLARIN
Keyword(s):  
Numerical Simulations ◽  
Chaotic Attractor ◽  
Essential Feature ◽  
State Variables ◽  
Synchronous State ◽  
Boundary Crisis ◽  
The Cross ◽  
Coupled Duffing Oscillators ◽  
Structurally Stable

Numerical simulations have been used to investigate the synchronization behavior of a unidirectionally coupled pair of double-well duffing oscillators (DDOs). The DDOs were simulated in their structurally stable chaotic zone and their state variables were found to completely synchronized. The essential feature of the transition to the synchronous state is shown to correspond to a boundary crisis in which the cross-well chaotic attractor is destroyed.

1.3 Computer Hardware: Principles and Potential

1981 ◽  
Vol 5 ◽  
pp. 9-13
Author(s):  
A. P. Dorey
Keyword(s):  
Integrated Circuits ◽  
Essential Feature ◽  
Computer Hardware ◽  
Computer Design ◽  
Physical Size ◽  
The Family ◽  
Technical Advances ◽  
Microelectronics Industry ◽  
Discrete Values ◽  
Computer Operation

The achievement of the microelectronics industry in integrating the components of a computer on to a few, or even a single, increasingly complex silicon chip has resulted in a reduction in price of the basic elements of a computer system by more than one hundred times. This technology has brought the cheap calculator which can now provide quite sophisticated programming functions that could only have been obtained with a computer occupying an equipment rack some few yean ago. The microprocessor is the most complex of the family of integrated circuits but its operation is not fundamentally different from that of its much larger predecessors, being a feat of technology rather than a new departure in computer design. It is the dramatic change in price and physical size, coupled with other associated technical advances such as low power consumption and reliability, that has made it possible for the use of computers to be considered in situations which could not reasonably be contemplated previously.Although computers include those that operate or continuous, or analogue, variables, the predominanl interest is in digital systems. These operate on discrete values of electrical signals that represent, in coded forms, data or the operations to be performed. These operations can be arithmetical or logical and may be combined into a sequence that constitutes a program. The notion of stored program control, where such a sequence is held in the memory of the machine, provides the essential feature of computer operation.

scholarly journals Master-Slave Topologies with Phase-Locked Loops

2020 ◽  
Vol 2020 ◽  
pp. 1-12
Author(s):  
José Roberto C. Piqueira
Keyword(s):  
Integrated Circuits ◽  
Communication Networks ◽  
Smart Grids ◽  
Essential Element ◽  
Recovery Process ◽  
Distribution Networks ◽  
Phase Locked Loops ◽  
Signal Recovery ◽  
Clock Signal ◽  
Clock Distribution

Since phase-locked loops (PLLs) were conceived by Bellescize in 1932, their presence has become almost mandatory in any telecommunication device or network, being the essential element to recover frequency and phase information. As the technology developed, PLL appeared in several applications, such as, dense communication networks, smart grids, electronic instrumentation, computational clusters, and integrated circuits. In all of these practical cases, isolated or networked PLLs are responsible for recovering the correct time basis and synchronizing the processes. According to the application needs, different clock distribution strategies were developed, with the master-slave being the simplest and most used choice. Considering that the master clock is obtained from a stable periodic oscillator, two topologies are studied: one-way, not considering clock feedback; and two-way master-slave, with the slave nodes providing clock feedback to the master. Here, these two cases are studied by using simulation strategies, presenting results about the clock signal recovery process in the presence of disturbances, indicating that master-slave clock distribution networks can be useful for networks with few nodes and a stable master oscillator with the one-way topology presenting better results than the two-way arrangement.

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