scholarly journals Delay Efficient 32-Bit Carry-Skip Adder

VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-8 ◽  
Author(s):  
Yu Shen Lin ◽  
Damu Radhakrishnan
Keyword(s):  
Critical Path ◽  
Cmos Technology ◽  
Look Ahead ◽  
Speed Up ◽  
Minimum Delay ◽  
Simulation Results ◽  
Carry Skip Adders ◽  
Block Sizes ◽  
Multiple Stages

The design of a 32-bit carry-skip adder to achieve minimum delay is presented in this paper. A fast carry look-ahead logic using group generate and group propagate functions is used to speed up the performance of multiple stages of ripple carry adders. The group generate and group propagate functions are generated in parallel with the carry generation for each block. The optimum block sizes are decided by considering the critical path into account. The new architecture delivers the sum and carry outputs in lesser unit delays than existing carry-skip adders. The adder is implemented in 0.25 m CMOS technology at 3.3 V. The critical delay for the proposed adder is 3.4 nanoseconds. The simulation results show that the proposed adder is 18 faster than the current fastest carry-skip adder.

Design of 25-Gb/s Half-Rate Clock and Data Recovery Circuit for Optical Communication

2013 ◽  
Vol 385-386 ◽  
pp. 1278-1281 ◽  
Author(s):  
Zheng Fei Hu ◽  
Ying Mei Chen ◽  
Shao Jia Xue
Keyword(s):  
Optical Communication ◽  
Input Data ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Voltage Controlled Oscillator ◽  
Output Data ◽  
Data Phase ◽  
Simulation Results

A 25-Gb/s clock and data recovery (CDR) circuit with 1:2 demultiplexer which incorporates a quadrature LC voltage-controlled-oscillator and a half-rate bang-bang phase detector is presented in this paper. A quadrature LC VCO is presented to generate the four-phase output clocks. A half-rate phase detector including four flip-flops samples the 25-Gb/s input data every 20 ps and alignes the data phase. The 25-Gb/s data are retimed and demultiplexed into two 12.5-Gb/s output data. The CDR is designed in TSMC 65nm CMOS Technology. Simulation results show that the recovered clock exhibits a peak-to-peak jitter of 0.524ps and the recovered data exhibits a peak-to-peak jitter of 1.2ps. The CDR circuit consumes 121 mW from a 1.2 V supply.

An Offset Reduction Technique for Latch Type Sense Amplifier in High Performance and High Density SRAM

2012 ◽  
Vol 542-543 ◽  
pp. 769-774
Author(s):  
Qun Ling Yu ◽  
Na Bai ◽  
Yan Zhou ◽  
Rui Xing Li ◽  
Jun Ning Chen ◽  
...  
Keyword(s):  
High Performance ◽  
Circuit Simulation ◽  
Cmos Technology ◽  
Optimal Operation ◽  
Reduction Technique ◽  
Total Speed ◽  
Sense Amplifier ◽  
Simulation Results ◽  
A New Technique ◽  
Total Energy Dissipation

A new technique for reducing the offset of latch-type sense amplifier has been proposed and effect of enable signal voltage upon latch-type sense amplifier offset in SRAM has been investigated in this paper. Circuit simulation results on both StrongARM and Double-tail topologies show that the standard deviation of offset can be reduced by 31.23% (StrongARM SA) and 25.2% (Double-tail SA) , respectively, when the voltage of enable signal reaches 0.6V in TSMC 65nm CMOS technology. For a column of bit-cell (1024 bit-cell), the total speed is improved by 14.98% (StrongARAM SA) and 22.26% (Double-tail SA) at the optimal operation point separately, and the total energy dissipation is reduced by 30.45% and 29.47% with this scheme.

A 10T Cell Design without Half Select Problem for Bit-Interleaving Architecture in 65nm CMOS

2013 ◽  
Vol 373-375 ◽  
pp. 1607-1611
Author(s):  
Hong Gang Zhou ◽  
Shou Biao Tan ◽  
Qiang Song ◽  
Chun Yu Peng
Keyword(s):  
Error Correction ◽  
Low Voltage ◽  
Cmos Technology ◽  
Soft Error ◽  
Error Correction Codes ◽  
Cell Design ◽  
Low Voltage Operation ◽  
Sram Cell ◽  
Simulation Results ◽  
Nanometer Regime

With the scaling of process technologies into the nanometer regime, multiple-bit soft error problem becomes more serious. In order to improve the reliability and yield of SRAM, bit-interleaving architecture which integrated with error correction codes (ECC) is commonly used. However, this leads to the half select problem, which involves two aspects: the half select disturb and the additional power caused by half-selected cells. In this paper, we propose a new 10T cell to allow the bit-interleaving array while completely eliminating the half select problem, thus allowing low-power and low-voltage operation. In addition, the RSNM and WM of our proposed 10T cell are improved by 21% and nearly one times, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology. We also conduct a comparison with the conventional 6T cell about the leakage simulation results, which show 14% of leakage saving in the proposed 10T cell.

scholarly journals Gm-Realization of Controlled-Gain Current Follower Transconductance Amplifier

2013 ◽  
Vol 2013 ◽  
pp. 1-8 ◽  
Author(s):  
Worapong Tangsrirat
Keyword(s):  
Current Mode ◽  
Cmos Technology ◽  
Current Transfer ◽  
Biquad Filter ◽  
Transconductance Amplifier ◽  
Current Follower ◽  
Dc Bias ◽  
Simulation Results ◽  
Supply Voltages ◽  
A Current

This paper describes the conception of the current follower transconductance amplifier (CFTA) with electronically and linearly current tunable. The newly modified element is realized based on the use of transconductance cells (Gms) as core circuits. The advantage of this element is that the current transfer ratios (iz/ipandix/iz) can be tuned electronically and linearly by adjusting external DC bias currents. The circuit is designed and analyzed in 0.35 μm TSMC CMOS technology. Simulation results for the circuit with ±1.25 V supply voltages show that it consumes only 0.43 mw quiescent power with 70 MHz bandwidth. As an application example, a current-mode KHN biquad filter is designed and simulated.

A 2.4GHz Radio-Over-Fiber Laser Diode Drive Amplifier in 0.18-um CMOS

2013 ◽  
Vol 433-435 ◽  
pp. 1463-1469 ◽  
Author(s):  
Yi Lin Zheng ◽  
Ying Mei Chen ◽  
Jian Wei Gong ◽  
Jian Guo Yao
Keyword(s):  
Laser Diode ◽  
Cmos Technology ◽  
Radio Over Fiber ◽  
Power Gain ◽  
Power Added Efficiency ◽  
Input And Output ◽  
Linear Amplifier ◽  
Simulation Results ◽  
On Chip ◽  
Dynamic Bias

The design of a 2.4GHz radio-over-fiber (ROF) laser diode drive amplifier using TSMC 0.18-um CMOS technology is presented in this paper. The proposed drive amplifier is a single-ended two-stage amplifier with the operating voltages of 1.8V and 3.3V. The technique of dynamic bias is employed to enhance linearity. The post simulation results show that the linear amplifier achieves the power gain of 26.26dB, the output 1dB compression point of 20.49dBm at 2.4GHz. The maximum power added efficiency (PAE) is 27.97%. The components are all on chip including the input and output matching network, and the die size is 1.065mm×0.73mm.

New Grounded and Floating Memristor-Less Meminductor Emulators Using VDTA and CDBA

2021 ◽  
pp. 2150283
Author(s):  
Nisha Yadav ◽  
Shireesh Kumar Rai ◽  
Rishikesh Pandey
Keyword(s):  
Adaptive Learning ◽  
Hysteresis Loops ◽  
Cmos Technology ◽  
Chaotic Oscillator ◽  
Simulation Tool ◽  
Analog Multiplier ◽  
Transconductance Amplifier ◽  
Simulation Results ◽  
Pinched Hysteresis

In this paper, new memristor-less meminductor emulators have been proposed using voltage differencing transconductance amplifier (VDTA), current differencing buffered amplifier (CDBA) and a grounded capacitor. The proposed decremental/incremental meminductor emulators have been realized in both grounded and floating types of configurations. In the proposed meminductor emulators, analog multiplier, memristor and passive resistors are not used which result in simpler configurations. The pinched hysteresis loops are maintained up to 2[Formula: see text]MHz for both decremental and incremental configurations of meminductor emulators. The behaviors of decremental and incremental meminductor emulators have been analyzed after applying input pulses. The obtained results verify the performances as decremental and incremental meminductor emulators. The simulation results have been obtained using Mentor Graphics Eldo simulation tool with 180[Formula: see text]nm CMOS technology parameters. To verify the performances of the proposed meminductor emulators, adaptive learning circuit and chaotic oscillator have been designed. The performances of the proposed meminductor emulators are compared with other meminductor emulators reported in the literature.

Automatic Circuit Design of CMOS Miller OTA Using Cuckoo Search Algorithm

2020 ◽  
Vol 11 (1) ◽  
pp. 36-44
Author(s):  
Pankaj P. Prajapati ◽  
Mihir V. Shah
Keyword(s):  
Circuit Design ◽  
Computer Aided Design ◽  
Search Algorithm ◽  
Fitness Function ◽  
Large Fraction ◽  
Cuckoo Search ◽  
Cmos Technology ◽  
Experimental Simulation ◽  
Automatic Design ◽  
Simulation Results

The circuit design of the CMOS based analog part of a mixed-signal integrated circuit (IC) needs a large fraction of the overall design cycle time. The automatic design of an analog circuit is inevitable, seeing recently development of System-on-Chip (SOC) design. This brings about the need to develop computer aided design (CAD) tools for automatic design of CMOS based analog circuits. In this article, a Cuckoo Search (CS) algorithm is presented for automatic design of a CMOS Miller Operational Transconductance Amplifier (OTA). The source code of the CS algorithm is developed using the C language. The Ngspice circuit simulator has been used as a fitness function creator and evaluator. A script file is written to provide an interface between the CS algorithm and the Ngspice simulator. BSIM3v3 MOSFET models with 0.18 µm and 0.35 µm CMOS technology have been used to simulate this circuit. The simulation results of this work are presented and compared with previous works reported in the literature. The experimental simulation results obtained by the CS algorithm satisfy all desired specifications for this circuit.

Risk Management of Construction Schedule by PERT with Monte Carlo Simulation

2014 ◽  
Vol 548-549 ◽  
pp. 1646-1650 ◽  
Author(s):  
Yang Liu ◽  
Yan Li
Keyword(s):  
Sensitivity Analysis ◽  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
Critical Path ◽  
Total Duration ◽  
Control Points ◽  
Schedule Management ◽  
Simulation Results ◽  
Critical Paths ◽  
Construction Schedule

It has been proved that the construction schedule management was an uncertain problem. Traditional CPM method was a good way to define the total duration and critical paths but can not solve uncertainty. The paper use CPM to define the duration and critical path firstly, then defined the parameters with Delphi and make Monte Carlo simulation. Through simulation results, it is found that the probability to finish the work on time was only 35.3%. The following step is to make sensitivity analysis, through the calculation, the work which has large influence was found and treat as key control points. It is proved that Monte Carlo simulation is useful to solve the problem of construction schedule management.

An Analytical Study on Jitter Accumulation in Interleaved Phase Frequency Detectors for High-Accuracy On-Chip Jitter Measurements

2013 ◽  
Vol 534 ◽  
pp. 197-205
Author(s):  
Kiichi Niitsu ◽  
Masato Sakurai ◽  
Naohiro Harigai ◽  
Daiki Hirabayashi ◽  
Daiki Oki ◽  
...  
Keyword(s):  
Power Supply ◽  
Analytical Study ◽  
Cmos Technology ◽  
High Accuracy ◽  
Spice Simulation ◽  
Supply Noise ◽  
Noise Injection ◽  
Simulation Results ◽  
On Chip ◽  
Frequency Detector

This work presents the analytical study on jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements. Jitter accumulation in phase frequency detector degrades the accuracy of on-chip jitter measurements, and required to be mitigated. In order to analyze and estimate the jitter accumulation in phase frequency detectors, SPICE simulation was performed with 65 nm CMOS technology. Simulation results show that, with a 50 mV power supply noise injection, jitter accumulation can be reduced from 1.03 ps to 0.49 ps (52% reduction) by using an interleaved architecture.

Low Power FGSRAM Cell Using Sleepy and LECTOR Technique

2016 ◽  
Vol 4 (2) ◽  
pp. 333 ◽  
Author(s):  
Kanan Bala Ray ◽  
Sushanta Kumar Mandal ◽  
Shivalal Patro
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Stability ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Floating Gate ◽  
Power Supply Voltage ◽  
Operation Analysis ◽  
Sram Cell ◽  
Simulation Results

<em>In this paper floating gate MOS (FGMOS) along with sleep transistor technique and leakage control transistor (LECTOR) technique has been used to design low power SRAM cell. Detailed investigation on operation, analysis and result comparison of conventional 6T, FGSRAM, FGSLEEPY, FGLECTOR and FGSLEEPY LECTOR has been done. All the simulations are done in Cadence Virtuoso environment on 45 nm standard CMOS technology with 1 V power supply voltage. Simulation results show that FGSLEEPY LECTOR SRAM cell consumes very low power and achieves high stability compared to conventional FGSRAM Cell</em>

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