scholarly journals A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic

VLSI Design ◽  
2007 ◽  
Vol 2007 ◽  
pp. 1-16 ◽  
Author(s):  
Andreas Hansson ◽  
Kees Goossens ◽  
Andrei Rădulescu
Keyword(s):  
Power Dissipation ◽  
Network On Chip ◽  
Path Selection ◽  
Objective Functions ◽  
Unified Approach ◽  
Slot Allocation ◽  
Worst Case ◽  
On Chip ◽  
Guaranteed Service ◽  
Key Steps

One of the key steps in Network-on-Chip-based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problems first map cores onto a topology and then route communication, using separate and possibly conflicting objective functions. In this paper, we present a unified single-objective algorithm, called Unified MApping, Routing, and Slot allocation (UMARS+). As the main contribution, we show how to couple path selection, mapping of cores, and channel time-slot allocation to minimize the network required to meet the constraints of the application. The time-complexity of UMARS+ is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder System-on-Chip, reducing area by 33%, power dissipation by 35%, and worst-case latency by a factor four over a traditional waterfall approach.

scholarly journals Bus Based Synchronization Method for CHIPPER Based NoC

2016 ◽  
Vol 2016 ◽  
pp. 1-11
Author(s):  
D. Muralidharan ◽  
R. Muthaiah
Keyword(s):  
Power Consumption ◽  
Network On Chip ◽  
System On Chip ◽  
Communication Delay ◽  
Worst Case ◽  
Synchronization Method ◽  
Area Overhead ◽  
On Chip

Network on Chip (NoC) reduces the communication delay of System on Chip (SoC). The main limitation of NoC is power consumption and area overhead. Bufferless NoC reduces the area complexity and power consumption by eliminating buffers in the traditional routers. The bufferless NoC design should include live lock freeness since they use hot potato routing. This increases the complexity of bufferless NoC design. Among the available propositions to reduce this complexity, CHIPPER based bufferless NoC is considered as one of the best options. Live lock freeness is provided in CHIPPER through golden epoch and golden packet. All routers follow some synchronization method to identify a golden packet. Clock based method is intuitively followed for synchronization in CHIPPER based NoCs. It is shown in this work that the worst-case latency of packets is unbearably high when the above synchronization is followed. To alleviate this problem, broadcast bus NoC (BBus NoC) approach is proposed in this work. The proposed method decreases the worst-case latency of packets by increasing the golden epoch rate of CHIPPER.

scholarly journals Network-On-Chip Topology Generation and Analysis For Transaction-Based Systems-on-Chip

2021 ◽  
Author(s):  
Victor. Dumitriu
Keyword(s):  
Design Method ◽  
Prediction Method ◽  
Network On Chip ◽  
Network Resources ◽  
Case Scenario ◽  
Worst Case ◽  
Networks On Chip ◽  
Analysis And Design ◽  
Systems On Chip ◽  
On Chip

The Network-on-Chip concept is emerging as a promising new method of addressing the communication requirements of complex Systems-on-Chip. However, network design at this level must take into consideration the specific communication protocols of on-chip components. This thesis presents a topology analysis and design method for networks-on-chip based on the transaction-oriented protocols common to on-chip systems. The generated topologies target the latency of critical links in the system, while the analysis method can predict the degree of contention in a system prior to the simulation phase. The proposed topologies are tested using various applications, including and MPEG4 Decoder, and are found to perform the same or better than regular topologies, while using less network resources. The contention prediction method is found to be accurate to within 27% in the worst case scenario.

scholarly journals Power and Signal-to-Noise Ratio Optimization in Mesh-Based Hybrid Optical Network-on-Chip using Semiconductor Optical Amplifiers

2019 ◽  
Vol 9 (6) ◽  
pp. 1251 ◽  
Author(s):  
Jun Yeong Jang ◽  
Min Su Kim ◽  
Chang-Lin Li ◽  
Tae Hee Han
Keyword(s):  
Optical Amplifiers ◽  
Signal To Noise Ratio ◽  
Optical Network ◽  
Semiconductor Optical Amplifiers ◽  
Network On Chip ◽  
Laser Source ◽  
Crosstalk Noise ◽  
Worst Case ◽  
And Performance ◽  
On Chip

To address the performance bottleneck in metal-based interconnects, hybrid optical network-on-chip (HONoC) has emerged as a new alternative. However, as the size of the HONoC grows, insertion loss and crosstalk noise increase, leading to excessive laser source output power and performance degradation. Therefore, we propose a low-power scalable HONoC architecture by incorporating semiconductor optical amplifiers (SOAs). An SOA placement algorithm is developed considering insertion loss and crosstalk noise. Furthermore, we establish a worst-case crosstalk noise model of SOA-enabled HONoC and induce optimized SOA gains with respect to power consumption and performance, respectively. Extensive simulations for worst-case signal-to-noise ratio (SNR) and power consumption are conducted under various traffic patterns and different network sizes. Simulation results show that the proposed SOA-enabled HONoC architecture and the associated algorithm help sustain the performance as network size increases without additional laser source power.

scholarly journals Network-On-Chip Topology Generation and Analysis For Transaction-Based Systems-on-Chip

2021 ◽  
Author(s):  
Victor. Dumitriu
Keyword(s):  
Design Method ◽  
Prediction Method ◽  
Network On Chip ◽  
Network Resources ◽  
Case Scenario ◽  
Worst Case ◽  
Networks On Chip ◽  
Analysis And Design ◽  
Systems On Chip ◽  
On Chip

The Network-on-Chip concept is emerging as a promising new method of addressing the communication requirements of complex Systems-on-Chip. However, network design at this level must take into consideration the specific communication protocols of on-chip components. This thesis presents a topology analysis and design method for networks-on-chip based on the transaction-oriented protocols common to on-chip systems. The generated topologies target the latency of critical links in the system, while the analysis method can predict the degree of contention in a system prior to the simulation phase. The proposed topologies are tested using various applications, including and MPEG4 Decoder, and are found to perform the same or better than regular topologies, while using less network resources. The contention prediction method is found to be accurate to within 27% in the worst case scenario.

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