scholarly journals Power and Signal-to-Noise Ratio Optimization in Mesh-Based Hybrid Optical Network-on-Chip using Semiconductor Optical Amplifiers

2019 ◽  
Vol 9 (6) ◽  
pp. 1251 ◽  
Author(s):  
Jun Yeong Jang ◽  
Min Su Kim ◽  
Chang-Lin Li ◽  
Tae Hee Han
Keyword(s):  
Optical Amplifiers ◽  
Signal To Noise Ratio ◽  
Optical Network ◽  
Semiconductor Optical Amplifiers ◽  
Network On Chip ◽  
Laser Source ◽  
Crosstalk Noise ◽  
Worst Case ◽  
And Performance ◽  
On Chip

To address the performance bottleneck in metal-based interconnects, hybrid optical network-on-chip (HONoC) has emerged as a new alternative. However, as the size of the HONoC grows, insertion loss and crosstalk noise increase, leading to excessive laser source output power and performance degradation. Therefore, we propose a low-power scalable HONoC architecture by incorporating semiconductor optical amplifiers (SOAs). An SOA placement algorithm is developed considering insertion loss and crosstalk noise. Furthermore, we establish a worst-case crosstalk noise model of SOA-enabled HONoC and induce optimized SOA gains with respect to power consumption and performance, respectively. Extensive simulations for worst-case signal-to-noise ratio (SNR) and power consumption are conducted under various traffic patterns and different network sizes. Simulation results show that the proposed SOA-enabled HONoC architecture and the associated algorithm help sustain the performance as network size increases without additional laser source power.

scholarly journals Detection and Monitoring Intra/Inter Crosstalk in Optical Network on Chip

2018 ◽  
Vol 8 (6) ◽  
pp. 4912
Author(s):  
Ahmed Jedidi
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Data Exchange ◽  
High Reliability ◽  
Optical Network ◽  
Network On Chip ◽  
Computer Applications ◽  
Multiprocessor System ◽  
Crosstalk Noise ◽  
On Chip

Multiprocessor system-on-chip (MPSoC) has become an attractive solution for improving the performance of single chip in objective to satisfy the performance growing exponentially of the computer applications as multimedia applications. However, the communication between the different processors’ cores presents the first challenge front the high performance of MPSoC. Besides, Network on Chip (NoC) is among the most prominent solution for handling the on-chip communication. Besides, NoC potential limited by physical limitation, power consumption, latency and bandwidth in the both case: increasing data exchange or scalability of Multicores. Optical communication offers a wider bandwidth and lower power consumption, based on, a new technology named Optical Network-on-Chip (ONoC) has been introduced in MPSoC. However, ONoC components induce the crosstalk noise in the network on both forms intra/inter crosstalk. This serious problem deteriorates the quality of signals and degrades network performance. As a result, detection and monitoring the impairments becoming a challenge to keep the performance in the ONoC. In this article, we propose a new system to detect and monitor the crosstalk noise in ONoC. Particularly, we present an analytic model of intra/inter crosstalk at the optical devices. Then, we evaluate these impairments in objective to present the motivation to detect and monitor crosstalk in ONoC, in which our system has the capability to detect, to localize, and to monitor the crosstalk noise in the whole network. This system offers high reliability, scalability and efficiency with time running time less than 20 ms.

scholarly journals Universal Method for Constructing Fault-Tolerant Optical Routers Using RRW

2021 ◽  
Vol 2021 ◽  
pp. 1-15
Author(s):  
Meaad Fadhel ◽  
Lei Huang ◽  
Huaxi Gu
Keyword(s):  
Fault Tolerant ◽  
Transmission Probability ◽  
Network On Chip ◽  
Universal Method ◽  
Crosstalk Noise ◽  
Worst Case ◽  
Backup Path ◽  
Optical Routers ◽  
On Chip ◽  
Backup Paths

High-speed data transmission enabled by photonic network-on-chip (PNoC) has been regarded as a significant technology to overcome the power and bandwidth constraints of electrical network-on-Chip (ENoC). This has given rise to an exciting new research area, which has piqued the public’s attention. Current on-chip architectures cannot guarantee the reliability of PNoC, due to component failures or breakdowns occurring, mainly, in active components such as optical routers (ORs). When such faults manifest, the optical router will not function properly, and the whole network will ultimately collapse. Moreover, essential phenomena such as insertion loss, crosstalk noise, and optical signal-to-noise ratio (OSNR) must be considered to provide fault-tolerant PNoC architectures with low-power consumption. The main purpose of this manuscript is to improve the reliability of PNoCs without exposing the network to further blocking or contention by taking the effect of backup paths on signals sent over the default paths into consideration. Thus, we propose a universal method that can be applied to any optical router in order to increase the reliability by using a reliable ring waveguide (RRW) to provide backup paths for each transmitted signal within the same router, without the need to change the route of the signal within the network. Moreover, we proposed a simultaneous transmission probability analysis for optical routers to show the feasibility of this proposed method. This probability analyzes all the possible signals that can be transmitted at the same time within the default and the backup paths of the router. Our research work shows that the simultaneous transmission probability is improved by 10% to 46% compared to other fault-tolerant optical routers. Furthermore, the worst-case insertion loss of our scheme can be reduced by 46.34% compared to others. The worst-case crosstalk noise is also reduced by 24.55%, at least, for the default path and 15.7%, at least, for the backup path. Finally, in the network level, the OSNR is increased by an average of 68.5% for the default path and an average of 15.9% for the backup path, for different sizes of the network.

scholarly journals Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures

2021 ◽  
Author(s):  
Anita Tino
Keyword(s):  
Tabu Search ◽  
Network On Chip ◽  
Computational Time ◽  
Multiprocessor System ◽  
Case Scenario ◽  
Worst Case ◽  
Multi Objective ◽  
And Performance ◽  
On Chip ◽  
Application Specific

Network-on-Chip (NoC) communication interconnects have emerged as a solution to complex heterogeneous core systems such as those found in Multiprocessor System-on-Chip architectures. Many previous works have used the objectives of power or performance during topology synthesis for regular or application specific based NoC design. However, given the crucial requirements and demands of future on-chip applications, it is imperative that designs consider both power and performance aspects, in addition to other important system constraints. Therefore, in order to address such issues, this thesis work presents a multi-objective Tabu search based topology synthesis technique for designing power and performance efficient Network-on-Chip architectures. The methodology incorporates an analytical and simulation approach in order to compromise between computational time and effort within the algorithm. Furthermore, this work also presents a novel approach for a power and performance tradeoff during contention and deadlock removal within synthesis. The proposed method was tested using seven different multimedia and network benchmark application, where results displayed an increase in performance and decrease in power dissipation in comparison to other previous application specific and regular mesh designs. The analysis method was successful during topology generation, yielding an overall accuracy rate deviation of 19.8% within the worst case scenario.

scholarly journals Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures

2021 ◽  
Author(s):  
Anita Tino
Keyword(s):  
Tabu Search ◽  
Network On Chip ◽  
Computational Time ◽  
Multiprocessor System ◽  
Case Scenario ◽  
Worst Case ◽  
Multi Objective ◽  
And Performance ◽  
On Chip ◽  
Application Specific

Network-on-Chip (NoC) communication interconnects have emerged as a solution to complex heterogeneous core systems such as those found in Multiprocessor System-on-Chip architectures. Many previous works have used the objectives of power or performance during topology synthesis for regular or application specific based NoC design. However, given the crucial requirements and demands of future on-chip applications, it is imperative that designs consider both power and performance aspects, in addition to other important system constraints. Therefore, in order to address such issues, this thesis work presents a multi-objective Tabu search based topology synthesis technique for designing power and performance efficient Network-on-Chip architectures. The methodology incorporates an analytical and simulation approach in order to compromise between computational time and effort within the algorithm. Furthermore, this work also presents a novel approach for a power and performance tradeoff during contention and deadlock removal within synthesis. The proposed method was tested using seven different multimedia and network benchmark application, where results displayed an increase in performance and decrease in power dissipation in comparison to other previous application specific and regular mesh designs. The analysis method was successful during topology generation, yielding an overall accuracy rate deviation of 19.8% within the worst case scenario.

CROSSTALK NOISE DETECTION AND MONITORING IN WDM-BASED OPTICAL NETWORK ON CHIP

2018 ◽  
Vol 7 (1) ◽  
pp. 1
Author(s):  
AHMED JEDIDI ◽  
MAHA EBRAHIM KHALIFA AL-SADOON ◽  
◽  
Keyword(s):  
Optical Network ◽  
Network On Chip ◽  
Noise Detection ◽  
Crosstalk Noise ◽  
On Chip

scholarly journals A Novel Laser Source Supply Scheme for Optical Network on Chip

IEEE Access ◽  
2019 ◽  
Vol 7 ◽  
pp. 25872-25877
Author(s):  
Zhuangzhuang Liu ◽  
Huaxi Gu ◽  
Kun Wang ◽  
Bowen Zhang ◽  
Kang Wang
Keyword(s):  
Optical Network ◽  
Network On Chip ◽  
Laser Source ◽  
On Chip
Sign in / Sign up

Export Citation Format

Share Document