scholarly journals Design of MOS-translinear Multiplier/Dividers in Analog VLSI

VLSI Design ◽  
2000 ◽  
Vol 11 (4) ◽  
pp. 321-329 ◽  
Author(s):  
Antonio J. Lopez-Martin ◽  
Alfonso Carlosena
Keyword(s):  
Dynamic Range ◽  
Geometric Mean ◽  
Current Mode ◽  
Building Blocks ◽  
Analog Vlsi ◽  
Cmos Process ◽  
Analog Multiplier ◽  
Wide Dynamic Range ◽  
Wide Range ◽  
Cascade Connection

A general framework for designing current-mode CMOS analog multiplier/divider circuits based on the cascade connection of a geometric-mean circuit and a squarer/divider is presented. It is shown how both building blocks can be readily obtained from a generic second-order MOS translinear loop. Various implementations are proposed, featuring simplicity, favorable precision and wide dynamic range. They can be successfully employed in a wide range of analog VLSI processing tasks. Experimental results of two versions, based on stacked and folded MOS-translinear loops and fabricated in a 2.4-μm CMOS process, are provided in order to verify the correctness of the proposed approach.

scholarly journals Toward High Throughput Core-CBCM CMOS Capacitive Sensors for Life Science Applications: A Novel Current-Mode for High Dynamic Range Circuitry

Sensors ◽  
2018 ◽  
Vol 18 (10) ◽  
pp. 3370 ◽  
Author(s):  
Saghi Forouhi ◽  
Rasoul Dehghani ◽  
Ebrahim Ghafar-Zadeh
Keyword(s):  
High Performance ◽  
Life Science ◽  
Dynamic Range ◽  
Current Mode ◽  
Capacitive Sensor ◽  
Oxide Semiconductor ◽  
Capacitance Measurement ◽  
Biological Research ◽  
Cmos Process ◽  
Capacitive Sensors

This paper proposes a novel charge-based Complementary Metal Oxide Semiconductor (CMOS) capacitive sensor for life science applications. Charge-based capacitance measurement (CBCM) has significantly attracted the attention of researchers for the design and implementation of high-precision CMOS capacitive biosensors. A conventional core-CBCM capacitive sensor consists of a capacitance-to-voltage converter (CVC), followed by a voltage-to-digital converter. In spite of their high accuracy and low complexity, their input dynamic range (IDR) limits the advantages of core-CBCM capacitive sensors for most biological applications, including cellular monitoring. In this paper, after a brief review of core-CBCM capacitive sensors, we address this challenge by proposing a new current-mode core-CBCM design. In this design, we combine CBCM and current-controlled oscillator (CCO) structures to improve the IDR of the capacitive readout circuit. Using a 0.18 μm CMOS process, we demonstrate and discuss the Cadence simulation results to demonstrate the high performance of the proposed circuitry. Based on these results, the proposed circuit offers an IDR ranging from 873 aF to 70 fF with a resolution of about 10 aF. This CMOS capacitive sensor with such a wide IDR can be employed for monitoring cellular and molecular activities that are suitable for biological research and clinical purposes.

scholarly journals Presynaptic and extrasynaptic regulation of posterior nucleus of thalamus

2017 ◽  
Vol 118 (1) ◽  
pp. 507-519 ◽  
Author(s):  
Anthony Park ◽  
Ying Li ◽  
Radi Masri ◽  
Asaf Keller
Keyword(s):  
Chronic Pain ◽  
Dynamic Range ◽  
Presynaptic Receptors ◽  
Activity Level ◽  
Regulatory Mechanisms ◽  
Wide Dynamic Range ◽  
Sensorimotor Processing ◽  
Wide Range ◽  
Maladaptive Plasticity ◽  
First Time

The posterior nucleus of thalamus (PO) is a higher-order nucleus involved in sensorimotor processing, including nociception. An important characteristic of PO is its wide range of activity profiles that vary across states of arousal, thought to underlie differences in somatosensory perception subject to attention and degree of consciousness. Furthermore, PO loses the ability to downregulate its activity level in some forms of chronic pain, suggesting that regulatory mechanisms underlying the normal modulation of PO activity may be pathologically altered. However, the mechanisms responsible for regulating such a wide dynamic range of activity are unknown. Here, we test a series of hypotheses regarding the function of several presynaptic receptors on both GABAergic and glutamatergic afferents targeting PO in mouse, using acute slice electrophysiology. We found that presynaptic GABAB receptors are present on both GABAergic and glutamatergic terminals in PO, but only those on GABAergic terminals are tonically active. We also found that release from GABAergic terminals, but not glutamatergic terminals, is suppressed by cholinergic activation and that a subpopulation of GABAergic terminals is regulated by cannabinoids. Finally, we discovered the presence of tonic currents mediated by extrasynaptic GABAA receptors in PO that are heterogeneously distributed across the nucleus. Thus we demonstrate that multiple regulatory mechanisms concurrently exist in PO, and we propose that regulation of inhibition, rather than excitation, is the more consequential mechanism by which PO activity can be regulated. NEW & NOTEWORTHY The posterior nucleus of thalamus (PO) is a key sensorimotor structure, whose activity is tightly regulated by inhibition from several nuclei. Maladaptive plasticity in this inhibition leads to severe pathologies, including chronic pain. We reveal here, for the first time in PO, multiple regulatory mechanisms that modulate synaptic transmission within PO. These findings may lead to targeted therapies for chronic pain and other disorders.

scholarly journals A low-voltage CMOS current-mode differential front-end for optical communications

2021 ◽  
Author(s):  
Bendong Sun
Keyword(s):  
Optical Communications ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Current Mode ◽  
Building Blocks ◽  
Switching Noise ◽  
Current Feedback ◽  
Fully Differential ◽  
Digital Circuitry

This thesis deals with the design of a low-voltage fully-differential CMOS current-mode preamplifier for optical communications. An in-depth comparative analysis of the building blocks of low-voltage CMOS current-mode circuits is carried out. Two new bandwidth enhancement techniques, namely inductor series-peaking and current feedback, are introduced and implemented in the design. The feedback also reduces the value of the series-peaking inductor. The minimum supply voltage of the amplifier is only one threshold voltage plus one pinch-off voltage. The preamplifier has a balanced differential topology such that the effect of bias dependent mismatches is minimized and the amplifier is insensitive to the switching noise caused by the digital circuitry. Negative differential current feedbacks are implemented to boost the bandwidth and increase the dynamic range.

scholarly journals A programmable energy efficient readout chip for a multiparameter highly integrated implantable biosensor system

2015 ◽  
Vol 13 ◽  
pp. 103-108 ◽  
Author(s):  
M. Nawito ◽  
H. Richter ◽  
A. Stett ◽  
J. N. Burghartz
Keyword(s):  
Circuit Simulation ◽  
Measurement Data ◽  
Building Blocks ◽  
Temperature Measurements ◽  
Full Duplex ◽  
Cmos Process ◽  
Internal Reference ◽  
Biosensor System ◽  
Wide Range ◽  
Measurement Results

Abstract. In this work an Application Specific Integrated Circuit (ASIC) for an implantable electrochemical biosensor system (SMART implant, Stett et al., 2014) is presented. The ASIC drives the measurement electrodes and performs amperometric measurements for determining the oxygen concentration, potentiometric measurements for evaluating the pH-level as well as temperature measurements. A 10-bit pipeline analog to digital (ADC) is used to digitize the acquired analog samples and is implemented as a single stage to reduce power consumption and chip area. For pH measurements, an offset subtraction technique is employed to raise the resolution to 12-bits. Charge integration is utilized for oxygen and temperature measurements with the capability to cover current ranges between 30 nA and 1 μA. In order to achieve good performance over a wide range of supply and process variations, internal reference voltages are generated from a programmable band-gap regulated circuit and biasing currents are supplied from a wide-range bootstrap current reference. To accommodate the limited available electrical power, all components are designed for low power operation. Also a sequential operation approach is applied, in which essential circuit building blocks are time multiplexed between different measurement types. All measurement sequences and parameters are programmable and can be adjusted for different tissues and media. The chip communicates with external unites through a full duplex two-wire Serial Peripheral Interface (SPI), which receives operational instructions and at the same time outputs the internally stored measurement data. The circuit has been fabricated in a standard 0.5-μm CMOS process and operates on a supply as low as 2.7 V. Measurement results show good performance and agree with circuit simulation. It consumes a maximum of 500 μA DC current and is clocked between 500 kHz and 4 MHz according to the measurement parameters. Measurement results of the on-chip ADC show a Differential Non Linearity (DNL) lower than 0.5 LSB, an Integral Non Linearity (INL) lower than 1 LSB and a Figure of Merit (FOM) of 6 pJ/conversion.

HIDING SECRET DATA THROUGH STEGANOGRAPHY IN VOIP

2017 ◽  
pp. 116-120
Author(s):  
SHILPA SUNIL WANKHADE ◽  
PROF. RAMESH V. SHAHABADE
Keyword(s):  
Information Hiding ◽  
Dynamic Range ◽  
Main Idea ◽  
Voice Over Internet Protocol ◽  
Secret Data ◽  
Wide Dynamic Range ◽  
Wide Range ◽  
Voice Packets ◽  
Voice Chat ◽  
The Voice

Steganography is an effective way of hiding secret data, by this means of protecting the data from unauthorized or unwanted viewing. Using cryptography technique will encrypt and decrypt message to provide better security. Cryptography protects the message from being read by unauthorized parties, steganography lets the sender conceal the fact that he has even sent a message. One of the new and promising communication medium that can be used as steganography is the Voice over Internet Protocol. VOIP covers a wide range of information hiding techniques. The main idea is to use free unused fields of VOIP protocols like TCP, UDP etc. By hiding one secret text into the cover speech using steganography we can get a stego speech, which sounds indistinguishable from the original cover speech. So even if the Hackers/crackers catch the audio packets on network, they would not notice that there is some secret text hidden inside it. To develop a Voice Chat Tool, this can also enable us to send secret data hidden inside the voice packets at the same time. We used LSB method of steganography and for better security we provide encryption to the message to be sent. There is no restriction on the length of message as more the communicators talk larger the file is sent. Human auditory system (HAS) operates over a wide dynamic range. It is challenging to hide secret data inside audio.

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