scholarly journals A VHDL Based Expert System for Hardware Synthesis

VLSI Design ◽  
1994 ◽  
Vol 1 (2) ◽  
pp. 113-126
Author(s):  
Sajjan G. Shiva ◽  
Judit U. Jones
Keyword(s):  
Expert System ◽  
Integrated Circuit ◽  
High Speed ◽  
Design Space Exploration ◽  
Semantic Network ◽  
Digital Circuit ◽  
Target System ◽  
Hardware Synthesis ◽  
Hardware Description ◽  
Representation Scheme

This paper describes an expert system for Hardware Synthesis. Details of the target digital system are input to the expert system using Very High Speed Integrated Circuit Hardware Description Language (VHDL). The VHDL representation is first translated to a knowledge representation scheme known as a ‘hologram’ which is a combination of rule, frame and semantic network representation schemes. The hologram representation of the target system is then input to the inference engine, which matches the target system to the Knowledge Base components and selects an appropriate set for implementation, and connects them creating a digital circuit. Some design examples are described. The expert system approach results in designs very close to designs from a human designer. In its present form, the system does not perform a design space exploration for alternate designs, but expects the designer to alter the VHDL representation, after observing the results from previous design cycles.

scholarly journals SYNTHESIS AND FPGA–IMPLEMENTATION BASED NEURAL TECHNIQUE OF A NONLINEAR ADC MODEL

2014 ◽  
pp. 27-33
Author(s):  
Mounir Bouhedda ◽  
Mokhtar Attari
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Description Language ◽  
Description Language ◽  
Analog To Digital ◽  
Field Programmable ◽  
Hardware Description ◽  
Nonlinear Analog ◽  
Very High

The aim of this paper is to introduce a new architecture using Artificial Neural Networks (ANN) in designing a 6-bit nonlinear Analog to Digital Converter (ADC). A study was conducted to synthesise an optimal ANN in view to FPGA (Field Programmable Gate Array) implementation using Very High-speed Integrated Circuit Hardware Description Language (VHDL). Simulation and tests results are carried out to show the efficiency of the designed ANN.

A modeling method of algorithm-hardware based on SysML

2021 ◽  
Author(s):  
Liu Yue ◽  
Zhao Chun ◽  
Zhang Lin
Keyword(s):  
Graphical Models ◽  
Integrated Circuit ◽  
High Speed ◽  
System Modeling ◽  
Modeling Method ◽  
Description Language ◽  
Hardware Description ◽  
Circuit And System ◽  
Graphical System ◽  
Hardware Circuit

In the process of complex product design, modeling in different fields and different disciplines is often involved. Designers often face many different development kits, platforms, and theories, among which significant differences exist. Especially in the process of algorithm-hardware implementation, it is necessary to have mastery of the knowledge including algorithm, hardware, circuit, and system engineering. In this paper, a modeling method of algorithm-hardware based on SysML is proposed to reduce the difficulty of algorithm-hardware modeling. By using the method, the designers who do not know the knowledge of hardware can also easily build the algorithm-hardware model. In this method, a method of graphical system modeling based on SysML is used, where the elements of the algorithm-hardware model are described by SysML graphical models. Then, the SysML graphical models are converted to Very-High-Speed Integrated Circuit Hardware Description Language. At last, a detecting algorithm of random number is complemented by the modeling method in this paper and the simulation results are presented at the conclusion.

scholarly journals High Throughput Implementation of the Keccak Hash Function Using the Nios-II Processor

Technologies ◽  
2020 ◽  
Vol 8 (1) ◽  
pp. 15
Author(s):  
Argyrios Sideris ◽  
Theodora Sanida ◽  
Minas Dasygenis
Keyword(s):  
Integrated Circuit ◽  
Hash Function ◽  
High Speed ◽  
Critical Role ◽  
Optimization Techniques ◽  
Floating Point ◽  
Throughput Optimization ◽  
Nios Ii ◽  
Hash Algorithm ◽  
Hardware Description

Presently, cryptographic hash functions play a critical role in many applications, such as digital signature systems, security communications, protocols, and network security infrastructures. The new standard cryptographic hash function is Secure Hash Algorithm 3 (SHA-3), which is not vulnerable to attacks. The Keccak algorithm is the winner of the NIST competition for the adoption of the new standard SHA-3 hash algorithm. In this work, we present hardware throughput optimization techniques for the SHA-3 algorithm using the Very High Speed Integrated Circuit Hardware Description Language (VHDL) programming language for all output lengths in the Keccak hash function (224, 256, 384 and 512). Our experiments were performed with the Nios II processor on the FPGA Arria 10 GX (10AX115N2P45E1SG). We applied two architectures, one without custom instruction and one with floating point hardware 2. Finally, we compare the results with other existing similar designs and found that the proposed design with floating point 2 optimizes throughput (Gbps) compared to existing FPGA implementations.

FPGA-Based In-Circuit Verification of Digital Systems

2011 ◽  
Vol 187 ◽  
pp. 362-367
Author(s):  
Fu Long Chen ◽  
Zhao Xia Zhu ◽  
Xiao Ya Fan
Keyword(s):  
Integrated Circuit ◽  
Circuit Complexity ◽  
Digital Circuit ◽  
Circuit Verification ◽  
Design Error ◽  
Circuit Component ◽  
Wide Scale ◽  
Hardware Description ◽  
Timing Simulation ◽  
Description Languages

In general hardware designers design integrated circuit with hardware description languages or schematic diagram. However the growth of circuit complexity makes circuit design error prone and time consuming. The resulting descriptions tend to be lengthy and hard to reason about. Therefore functional simulation, timing simulation and in-circuit test are three essential steps to ensure that the designed circuit is correct. This paper presents a method of in-circuit verification on FPGA using UART communication between the computer and the FPGA board. Through UART, designers can convert the parallel input vector into a set of serial stimulus signals and send them to the FPGA board, and also can receive the feedback serial signals from the FPGA board and reconvert them into a parallel output vector. Given the input and output ports of the verified circuit component, a verification platform based on UART communication will be customized automatically by the in-circuit verification platform generator. This breaks the constraint of the FPGA board's limited pins and supports wide-scale input/output vectors and can be applied in in-circuit test of digital circuit.

Power and Vibration of Electrostatic Precipitator Control Based on FPGA

2014 ◽  
Vol 1037 ◽  
pp. 244-247
Author(s):  
Zi Sheng Zhang ◽  
Chun Sheng Wang ◽  
Yi Wang ◽  
Zhan You Wang ◽  
Deng Yuan Song
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Electrostatic Precipitator ◽  
Description Language ◽  
Simulation Test ◽  
High Voltage Power Supply ◽  
Optimization Control ◽  
Field Programmable ◽  
Hardware Description ◽  
Fpga Chip

In order to improve the automation level of the electrostatic precipitator, we used Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) language to compile, emulate and optimize the control system of power source and vibration. In the design of Quartus platform, we used EP1C3T144C8 Field Programmable Gate Array (FPGA) chip to realize high voltage power supply, alarm and protection system. We also realized the compilation and simulation test of each part’s function of 20 s rapping and 40 min rapping cycle. At the same time, we recorded the waveform of simulation. It demonstrated that the validity of the relevant VHDL compilation. We used this method to achieve the optimization control of the electrostatic precipitator operating parameters. It has a strong practicability.

scholarly journals Design and Implementation of Radix 8 Booth Encoding Multiplier for Low Area and High-Speed Applications

2021 ◽  
Vol 9 (12) ◽  
pp. 862-864
Author(s):  
Mutyala Sri Anantha Lakshmi
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Description Language ◽  
Delay Reduction ◽  
Low Area ◽  
Booth Multiplier ◽  
Design And Implementation ◽  
Area Reduction ◽  
Hardware Description ◽  
Very High

Abstract: In this paper, we present the design and implementation of the Radix 8 Booth Encoding Multiplier. There are many multipliers in existence in which Radix 8 Booth Encoding Multiplier offers a decrease in area and provides high speed due to its diminution in the number of partial products. This project is designed and simulated on Xilinx ISE 14.7 version software using VHDL (Very High Speed Integrated Circuit Hardware Description Language). Simulation results show area reduction by 33.4% and delay reduction by 45.9% as compared to the conventional method. Keywords: Booth Multiplier, Radix 8, Partial Product

scholarly journals Performance Investigation of Digital Lowpass IIR Filter Based on Different Platforms

2021 ◽  
Vol 12 (2) ◽  
pp. 105-111
Author(s):  
Raaed Faleh Hassan
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Filter Design ◽  
Basic Unit ◽  
Infinite Impulse Response ◽  
Design Algorithm ◽  
System Generator ◽  
Iir Filter ◽  
Hardware Description ◽  
And Performance

The work presented in this paper illuminates the design and simulation of a recursive or Infinite Impulse Response (IIR) filter. The proposed design algorithm employs the Genetic Algorithm to determine the filter coefficients to satisfy the required performance. The effectiveness of different platforms on filter design and performance has been studied in this paper. Three different platforms are considered to implement and verify the designed filter’s work through simulation. The first platform is the MATLAB/SIMULINK software package used to implement the Biquad form filter. This technique is the basis for the software implementation of the designed IIR filter. The HDL – Cosimulation technique is considered the second one; it inspired to take advantage of the existing tools in SIMULINK to convert the designed filter algorithm to the Very high-speed integrated circuit Hardware Description Language (VHDL) format. The System Generator is employed as the third technique, in which the designed filter is implemented as a hardware structure based on basic unit blocks provided by Xilinx System Generator. This technique facilitates the implementation of the designed filter in the FPGA target device. Simulation results show that the performance of the designed filter is remarkably reliable even with severe noise levels.

Sign in / Sign up

Export Citation Format

Share Document