Origin of the Alternative Current (AC-) Gate Bias Improving the NBIS Stability of IGZO TFTs

2015 ◽  
Vol 4 (12) ◽  
pp. Q66-Q68 ◽  
Author(s):  
M. P. Hung ◽  
D. Wang ◽  
M. Furuta
Keyword(s):  
Gate Bias ◽  
Alternative Current

Carrier Redistribution Analysis of Gate-Biased SiC Power-MOSFET Using Super-Higher-Order Scanning Nonlinear Dielectric Microscopy

2015 ◽  
Author(s):  
Norimichi Chinone ◽  
Yasuo Cho
Keyword(s):  
Cross Section ◽  
Measurement System ◽  
Higher Order ◽  
Depletion Layer ◽  
Gate Bias ◽  
Power Mosfet ◽  
Nonlinear Dielectric ◽  
Voltage Dependent ◽  
Carrier Redistribution ◽  
Source Voltage

Abstract Gate-bias dependent depletion layer distribution and carrier distributions in cross-section of SiC power MOSFET were measured by newly developed measurement system based on super-higher-order scanning nonlinear dielectric microscope. The results visualized gate-source voltage dependent redistribution of depletion layer and carrier.

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

2020 ◽  
Vol 13 ◽  
Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu
Keyword(s):  
Monte Carlo ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Cmos Inverter ◽  
Back Gate ◽  
Random Dopant Fluctuation ◽  
Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

Demonstration of the enhancement of gate bias and ionic strength in electric-double-layer field-effect-transistor biosensors

2021 ◽  
Vol 334 ◽  
pp. 129567
Author(s):  
Chang-Run Wu ◽  
Shin-Li Wang ◽  
Po-Hsuan Chen ◽  
Yu-Lin Wang ◽  
Yu-Rong Wang ◽  
...  
Keyword(s):  
Ionic Strength ◽  
Double Layer ◽  
Electric Double Layer ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Gate Bias ◽  
Effect Transistor

scholarly journals Performance Optimization of Nitrogen Dioxide Gas Sensor Based on Pd-AlGaN/GaN HEMTs by Gate Bias Modulation

Micromachines ◽  
2021 ◽  
Vol 12 (4) ◽  
pp. 400
Author(s):  
Van Cuong Nguyen ◽  
Kwangeun Kim ◽  
Hyungtak Kim
Keyword(s):  
Gas Sensors ◽  
Performance Optimization ◽  
Response Times ◽  
High Electron Mobility Transistors ◽  
High Electron ◽  
Gate Bias ◽  
High Electron Mobility ◽  
Electron Mobility Transistors ◽  
Gan Hemts ◽  
Sensing Characteristics

We investigated the sensing characteristics of NO2 gas sensors based on Pd-AlGaN/GaN high electron mobility transistors (HEMTs) at high temperatures. In this paper, we demonstrated the optimization of the sensing performance by the gate bias, which exhibited the advantage of the FET-type sensors compared to the diode-type ones. When the sensor was biased near the threshold voltage, the electron density in the channel showed a relatively larger change with a response to the gas exposure and demonstrated a significant improvement in the sensitivity. At 300 °C under 100 ppm concentration, the sensor’s sensitivities were 26.7% and 91.6%, while the response times were 32 and 9 s at VG = 0 V and VG = −1 V, respectively. The sensor demonstrated the stable repeatability regardless of the gate voltage at a high temperature.

Study of Modulation in GaAs Misfets with LT-GaAs as a Gate Insulator

1991 ◽  
Vol 241 ◽  
Author(s):  
L.-W. Yin ◽  
J. Ibbetson ◽  
M. M. Hashemi ◽  
W. Jiang ◽  
S.-Y. Hu ◽  
...  
Keyword(s):  
Low Temperature ◽  
Gaas Layer ◽  
Gate Insulator ◽  
Gate Bias ◽  
Channel Current ◽  
Turn On ◽  
Dc Characteristics ◽  
Low Temperature Gaas ◽  
Channel Separation ◽  
Lt Gaas

ABSTRACTDC characteristics of a GaAs MISFET structure using low-temperature GaAs (LTGaAs) as the gate insulator were investigated. MISFETs with different gate to channel separation (d) were fabricated. The dependence of four important device parameters such as gate-drain breakdown voltage (VBR), channel current at zero gate bias (Idss), transconductance (gm), and gate-drain turn-on voltage (Von) on the gate insulator thickness were analyzed. It was observed that (a) in terms of Idss and gin, the LT-GaAs gate insulator behaves like an undoped regular GaAs layer and (b) in terms of VBR and Von, the LT-GaAs gate insulator behaves as a trap dominated layer.

Development of 1200 V, 3.7 mΩ-cm2 4H-SiC DMOSFETs for Advanced Power Applications

2012 ◽  
Vol 717-720 ◽  
pp. 1059-1064 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Lin Cheng ◽  
Sarit Dhar ◽  
Craig Capell ◽  
Charlotte Jonas ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Room Temperature ◽  
Voltage Drop ◽  
Drain Current ◽  
Subthreshold Swing ◽  
Active Area ◽  
Gate Bias ◽  
Forward Voltage ◽  
Recent Developments ◽  
Forward Voltage Drop

We present our recent developments in 4H-SiC power DMOSFETs. 4H-SiC DMOSFETs with a room temperature specific on-resistance of 3.7 mΩ-cm2 with a gate bias of 20 V, and an avalanche voltage of 1550 V with gate shorted to source, was demonstrated. A threshold voltage of 3.5 V was extracted from the power DMOSFET, and a subthreshold swing of 200 mV/dec was measured. The device was successfully scaled to an active area of 0.4 cm2, and the resulting device showed a drain current of 377 A at a forward voltage drop of 3.8 V at 25oC.

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